HD6412240 RENESAS [Renesas Technology Corp], HD6412240 Datasheet - Page 14

• Manufacturer Part Number: HD6412240
• Description: Renesas 16-Bit Single-Chip Microcomputer H8S Family / H8S/2200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

8.13.2 Register
Configuration
8.14 Handling of
Unused Pins
9.2.1 Timer Control
Register (TCR)
9.2.5 Timer Status
Register (TSR)
Rev.3.00 Mar. 26, 2007 Page xiv of xlii
REJ09B0355-0300
Item
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Page Revision (See Manual for Details)
Port G Data Direction Register (PGDDR)
Description amended
... an undefined value will be read. PGDDR cannot be modified.
This register is a write-only register, and cannot be written by bit
manipulation instruction. For details, see section 2.10.4, Access
Methods for Registers with Write-Only Bits. PGDDR is initialized
by a power-on reset ...
Section 8.14 added
Bits 4 and 3 Clock Edge 1 and 0 (CKEG1, CKEG0)
Note amended
Note: Internal clock edge selection is valid when the input clock
is /4 or slower. If /1 is selected as the input clock, this setting is
ignored and count at falling edge of is selected.
Bit 3 Input Capture/Output Compare Flag D (TGFD)
Description amended
[Clearing conditions]
Bit 2 Input Capture/Output Compare Flag C (TGFC)
Description amended
[Clearing conditions]
Bit 1 Input Capture/Output Compare Flag B (TGFB)
Description amended
[Clearing conditions]
When DTC is activated by TGID interrupt while DISEL bit of
MRB in DTC is 0 with the transfer counter not being 0.
When 0 is written to TGFD after reading TGFD = 1
When DTC is activated by TGIC interrupt while DISEL bit of
MRB in DTC is 0 with the transfer counter not being 0.
When 0 is written to TGFC after reading TGFC = 1
When DTC is activated by TGIB interrupt while DISEL bit of
MRB in DTC is 0 with the transfer counter not being 0.
When 0 is written to TGFB after reading TGFB = 1