HD6412240 RENESAS [Renesas Technology Corp], HD6412240 Datasheet - Page 283

• Manufacturer Part Number: HD6412240
• Description: Renesas 16-Bit Single-Chip Microcomputer H8S Family / H8S/2200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Table 8.11 Port A Registers
Notes: 1. Value of bits 3 to 0.
Port A Data Direction Register (PADDR)
Bit
Initial value
R/W
PADDR is an 8-bit write-only register, the individual bits of which specify input or output for the
pins of port A. Bits 7 to 4 are reserved. PADDR cannot be read; if it is, an undefined value will be
read. PADDR cannot be modified.
This register is a write-only register, and cannot be written by bit manipulation instruction. For
details, see section 2.10.4, Access Methods for Registers with Write-Only Bits.
PADDR is initialized to H'0 (bits 3 to 0) by a power-on reset and in hardware standby mode. It
retains its prior state after a manual reset, and in software standby mode. The OPE bit in SBYCR
is used to select whether the address output pins retain their output state or become high-
impedance when a transition is made to software standby mode.
Name
Port A data direction register
Port A data register
Port A register
Port A MOS pull-up control register
Port A open-drain control register
Modes 1, 2, 3, and 7
Setting a PADDR bit to 1 makes the corresponding port A pin an output port, while clearing
the bit to 0 makes the pin an input port.
Note: Modes 2, 3, and 7 cannot be used in the H8S/2240.
Modes 4 and 5
The corresponding port A pins are address outputs irrespective of the value of bits PA3DDR to
PA0DDR.
2. Lower 16 bits of the address.
:
:
:
Undefined
—
—
7
Undefined
—
—
6
PADDR
PAPCR
Abbreviation
PADR
PORTA
PAODR
Undefined
—
—
5
Undefined
—
—
4
R/W
W
R/W
R
R/W
R/W
Rev.3.00 Mar. 26, 2007 Page 241 of 772
PA3DDR
W
3
0
H'0
H'0
Initial Value*
H'0
Undefined
H'0
PA2DDR
W
2
0
Section 8 I/O Ports
PA1DDR
1
REJ09B0355-0300
W
1
0
H'FEB9
Address*
H'FF69
H'FF59
H'FF70
H'FF77
PA0DDR
W
0
0
2