HD6412240 RENESAS [Renesas Technology Corp], HD6412240 Datasheet - Page 480

• Manufacturer Part Number: HD6412240
• Description: Renesas 16-Bit Single-Chip Microcomputer H8S Family / H8S/2200 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 12 Serial Communication Interface (SCI)
Serial data transmission (asynchronous mode): Figure 12.5 shows a sample flowchart for serial
transmission.
The following procedure should be used for serial data transmission.
Rev.3.00 Mar. 26, 2007 Page 438 of 772
REJ09B0355-0300
and clear TDRE flag in SSR to 0
Write transmit data to TDR
Read TDRE flag in SSR
Read TEND flag in SSR
Clear TE bit in SCR to 0
All data transmitted?
Start transmission
Clear DR to 0 and
Break output?
set DDR to 1
Figure 12.5 Sample Serial Transmission Flowchart
Initialization
TDRE = 1?
TEND = 1?
<End>
Yes
Yes
Yes
Yes
No
No
No
No
[1]
[2]
[3]
[4]
[1] SCI initialization:
[2] SCI status check and transmit data
[3] Serial transmission continuation
[4] Break output at the end of serial
Note: * The case, in which the DTC
The TxD pin is automatically
designated as the transmit data
output pin.
After the TE bit is set to 1, a frame
of 1s is output, and transmission is
enabled.
write:
Read SSR and check that the
TDRE flag is set to 1, then write
transmit data to TDR and clear the
TDRE flag to 0.
procedure:
To continue serial transmission,
read 1 from the TDRE flag to
confirm that writing is possible,
then write data to TDR, and then
clear the TDRE flag to 0. Checking
and clearing of the TDRE flag is
automatic when the DTC * is
activated by a transmit data
empty interrupt (TXI) request, and
data is written to TDR.
transmission:
To output a break in serial
transmission, set DDR for the port
corresponding to the TxD pin to 1,
clear DR to 0, then clear the TE bit
in SCR to 0.
automatically checks and
clears the TDRE flag, occurs
only when DISEL in DTC is 0
with the transfer counter not
being 0. Therefore, the TDRE
flag should be cleared by CPU
when DISEL is 1, or when
DISEL is 0 with the transfer
counter being 0.