TMPA901CMXBG Toshiba, TMPA901CMXBG Datasheet - Page 849

• Manufacturer Part Number: TMPA901CMXBG
• Description: Microcontrollers (MCU) 32-bit RISC MCU 16kb ARM926EJ 16kb 200Mhz
• Manufacturer: Toshiba

Specifications of TMPA901CMXBG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): -
• Rom Type: ROMless
• Ram (kbytes): 32
• Number Of Pins: 177
• Package: BGA
• Vcc: 3V
• Tft Lcd Controller: Y
• Touchscreen Controller: Y
• Usb Host Fs With Phy: Y
• Usb Device Hs With Phy: Y
• Sd Host Controller: -
• Cmos Image Sensor Interface: -
• I2s: 1
• Ssp (ch) Spi: 1
• I2mc/sio (ch): 1
• Uart/sio (ch): 2
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 8
• 10-bit Ad Converter: 4
• 12-bit Da Converter: -
• 16-bit Timer / Counter: 6
• Real Time Clock: Y
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Low-power Modes: Y
• Lead Free Status / Rohs Status: Details

AC measurement conditions:
SPxCLK Period (Master)
SPxCLK Period (Slave)
SPxCLK rise up time
SPxCLK fall down time
Master mode: SPxCLK low level pulse width
Master mode: SPxCLK high level pulse width
Master Mode:
Master Mode:
Master Mode:
Master Mode:
Master Mode:
Slave mode:
Slave mode:
Slave mode:
Slave mode:
Slave mode:
Slave mode: SPxCLK low level pulse width
Slave mode: SPxCLK high level pulse width
Load capacitance CL
4.3.7
SPxCLK rise/fall to output data valid
SPxCLK rise/fall to output data hold
SPxCLK rise/fall to input data valid delay time
SPxCLK rise/fall to input data hold
SPxFSS valid to SPxCLK rise/fall
SPxCLK rise/fall to output data valid delay time
SPxCLK rise/fall to output data hold
SPxCLK rise/fall to input data valid delay time
SPxCLK rise/fall to input data hold
SPxFSS valid to SPxCLK rise/fall
Note1: Baud rate Clock is set under below condition
Note: The “Equation” column in the table shows the specifications under the conditions DVCC3IO 3.0 to 3.6 V and
AC measurement conditions
Master mode
Slave Mode
SSP Controller
m
Output level: High
Input level: High
<CPSDVR> is set only even number and “m” must set during 65204
n
The letter “T” used in the equations in the table represents the period of internal bus frequency (f
which is one-half of the CPU clock (f
DVCC1A
70 degree.
to 85 degree.
The internal bus cycle is T=10ns minimum value when the guaranteed temperature is 0 to
The internal bus cycle is T=13.3ns minimum value when the guaranteed temperature is -20
Parameter
(<CPSDVSR>
f
PCLK
25 pF
/SPxCLK (65204
DVCC1B
0.9
0.7
DVCC1C
(1
DVCC3IO, Low
DVC3IOM, Low
<SCR>))
TMPA901CM- 848
n
1.4 to 1.6 V.
Symbol
t
t
t
t
t
t
t
t
t
t
t
ODSM
ODHM
t
t
t
ODSS
ODHS
OFSM
Note1)
WHM
IDSM
IDHM
OFSS
WLM
WHS
IDSS
IDHS
12 )
WLS
T
FCLK
T
t
t
r
m
f
s
f
).
PCLK
0.1 DVCC3IO
However more than
0.3
/SPxCLK
(m)T / 2 - 7.0
(m)T / 2 –7.0
(n)T /2
(n)T / 2 - 7.0
(n)T / 2 - 7.0
(m)T/2 -10
(3T)
(m)T -10
DVCC3IO
(m)T
50ns
Min
(n)T
(n)T
5.0
Equation
10
(2T)
(n)T /2 (3T)
(m)T /2 - 20
m
(m)T
(3T)
- 10.0
Max
10.0
10.0
15.0
2
25
10
100MHz
PCLK
(m=6
10.0
50 70
n=12)
120.0
60.0
10.0
10.0
23.0
23.0
53.0
53.0
15.0
20.0
55.0
80.0
80.0
40.0
120
5.0
TMPA901CM
2010-07-29
52.5 72.5
96MHz
PCLK
n=12)
(m=6
125.0
62.5
10.0
10.0
24.3
24.3
55.5
55.5
15.0
21.3
11.2
56.3
83.3
83.8
41.3
125
5.0
PCLK
),
Unit
ns