TMPA901CMXBG Toshiba, TMPA901CMXBG Datasheet - Page 31

• Manufacturer Part Number: TMPA901CMXBG
• Description: Microcontrollers (MCU) 32-bit RISC MCU 16kb ARM926EJ 16kb 200Mhz
• Manufacturer: Toshiba

Specifications of TMPA901CMXBG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): -
• Rom Type: ROMless
• Ram (kbytes): 32
• Number Of Pins: 177
• Package: BGA
• Vcc: 3V
• Tft Lcd Controller: Y
• Touchscreen Controller: Y
• Usb Host Fs With Phy: Y
• Usb Device Hs With Phy: Y
• Sd Host Controller: -
• Cmos Image Sensor Interface: -
• I2s: 1
• Ssp (ch) Spi: 1
• I2mc/sio (ch): 1
• Uart/sio (ch): 2
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 8
• 10-bit Ad Converter: 4
• 12-bit Da Converter: -
• 16-bit Timer / Counter: 6
• Real Time Clock: Y
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Low-power Modes: Y
• Lead Free Status / Rohs Status: Details

3.2.6
3.2.7
TMS and TDI are sampled on the rising edge of
Data is scanned in serially.
TCK.
115
3
TCK
cells connected to the input and output pads on the TMPA901CM.
boundary scan register is shifted out on the TDO output.
TCK. These pins control a test by communicating the serial test data and instructions.
register, bypass register or boundary scan register) on the TDI pin, or it is scanned out from
one of these three registers on the TDO pin.
The TCK input is a special test clock that allows serial JTAG data to be shifted
synchronously, independent of any chip-specific or system clocks.
signal. Data on the TDO pin changes on the falling edge of the TCK clock signal.
Boundary Scan Register
Test Access Port (TAP)
processor except some analog outputs and control signals. The pins of the TMPA901CM
allow any pattern to be driven by scanning the data into the boundary scan register in the
Shift-DR state. Incoming data to the processor is examined by enabling the boundary scan
register and shifting the data when the BSR is in the Capture-DR state.
Instruction register
The boundary scan register provides all the inputs and outputs of the TMPA901CM
The boundary scan register is a single, 231-bit-wide, shift register-based path containing
The TDI input is loaded to the LSB of the boundary scan register. The MSB of the
The Test Access Port (TAP) consists of the five signal pins: TRSTn, TDI, TDO, TMS and
As Figure 3.2.5 shows, data is serially scanned into one of the three registers (instruction
The TMS input controls the state transitions of the main TAP controller state machine.
Data on the TDI and TMS pins are sampled on the rising edge of the TCK input clock
Bypass register
Boundary scan
register
0
0
0
Figure 3.2.5 JTAG Test Access Port
TMPA901CM- 30
TMS pin
TDI pin
3
115
Instruction register
TDO is sampled on the falling edge of TCK.
Bypass register
Boundary scan
register
0
Data is scanned out serially.
0
0
TMPA901CM
2010-07-29
TDO pin