TMPA901CMXBG Toshiba, TMPA901CMXBG Datasheet - Page 414

• Manufacturer Part Number: TMPA901CMXBG
• Description: Microcontrollers (MCU) 32-bit RISC MCU 16kb ARM926EJ 16kb 200Mhz
• Manufacturer: Toshiba

Specifications of TMPA901CMXBG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): -
• Rom Type: ROMless
• Ram (kbytes): 32
• Number Of Pins: 177
• Package: BGA
• Vcc: 3V
• Tft Lcd Controller: Y
• Touchscreen Controller: Y
• Usb Host Fs With Phy: Y
• Usb Device Hs With Phy: Y
• Sd Host Controller: -
• Cmos Image Sensor Interface: -
• I2s: 1
• Ssp (ch) Spi: 1
• I2mc/sio (ch): 1
• Uart/sio (ch): 2
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 8
• 10-bit Ad Converter: 4
• 12-bit Da Converter: -
• 16-bit Timer / Counter: 6
• Real Time Clock: Y
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Low-power Modes: Y
• Lead Free Status / Rohs Status: Details

Receive time out
interrupt enable (RTIM)
Receive time out
interrupt (RTINTR)
Receive FIFO
Empty flag (RNE)
Internal
counter enable
SP0CLK
(5) DMAC
The SSP provides an interface to connect to a DMA controller.
(c) Timeout interrupt
(d) Receive overrun interrupt
(e) Combined interrupt
the SSP has remained idle for a fixed duration of 32-bit period (bit rate). This
mechanism ensures that the user is aware that data is still present in the receive
FIFO and requires servicing. The timeout interrupt is generated both in master and
slave modes. When the timeout interrupt is generated, read all the data in the
receive FIFO. Data can be transmitted/received without reading all the data in the
receive FIFO provided that the receive FIFO has empty space for receiving the data
to be transmitted. The timeout interrupt is cleared when a transfer is started. If a
transfer is performed when the receive FIFO is full, the timeout interrupt is cleared
and the overrun interrupt is generated.
received, the receive overrun interrupt is asserted immediately after the completion
of the current transfer. Once the receive overrun error occurs, any subsequent data
received (including the 9th data frame) is invalid and discarded. However, if the
data in the receive FIFO is read while the 9th data frame is being received (before
the receive overrun interrupt occurs), the 9th data frame is written into the receive
FIFO as valid data. To perform proper transfer operation after the receive overrun
error occurred, write 1 to the receive overrun interrupt clear register and then read
all the data in the receive FIFO. Data can be transmitted/received without reading
all the data in the receive FIFO provided that the receive FIFO has empty space for
receiving the data to be transmitted. If the receive FIFO is not read (when it is not
empty) for a fixed duration of 32-bit period (bit rate) after the receive overrun
interrupt has been cleared, the timeout interrupt is generated.
a single interrupt. The combined interrupt INTS [12] is asserted if any of the four
interrupts is asserted.
The receive timeout interrupt is asserted when the receive FIFO is not empty and
When the receive FIFO is already full and an additional (9th) data frame is
The individual masked sources of the above four interrupts are also combined into
TMPA901CM- 413
Transfering data
Bit rate x 32
TMPA901CM
2010-07-29