TMPA901CMXBG Toshiba, TMPA901CMXBG Datasheet - Page 781

• Manufacturer Part Number: TMPA901CMXBG
• Description: Microcontrollers (MCU) 32-bit RISC MCU 16kb ARM926EJ 16kb 200Mhz
• Manufacturer: Toshiba

Specifications of TMPA901CMXBG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): -
• Rom Type: ROMless
• Ram (kbytes): 32
• Number Of Pins: 177
• Package: BGA
• Vcc: 3V
• Tft Lcd Controller: Y
• Touchscreen Controller: Y
• Usb Host Fs With Phy: Y
• Usb Device Hs With Phy: Y
• Sd Host Controller: -
• Cmos Image Sensor Interface: -
• I2s: 1
• Ssp (ch) Spi: 1
• I2mc/sio (ch): 1
• Uart/sio (ch): 2
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 8
• 10-bit Ad Converter: 4
• 12-bit Da Converter: -
• 16-bit Timer / Counter: 6
• Real Time Clock: Y
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Low-power Modes: Y
• Lead Free Status / Rohs Status: Details

Read/Write
(HCD)
Read/Write
(HC)
Read/Write
(HCD)
Read/Write
(HC)
bit Symbol
Reset state
bit Symbol
Reset state
[31:18]
[17:16]
[15:4]
[3]
Bit
3.
issued by the Host Controller Driver, as well as reflecting the current status of the Host
Controller. To the Host Controller Driver, it appears to be a "write to set" register. The Host
Controller must ensure that bits written as 1 become set in the register while bits written
as 0 remain unchanged in the register. The Host Controller Driver may issue multiple
distinct commands to the Host Controller without concern for corrupting previously issued
commands. The Host Controller Driver has normal read access to all bits.
Controller has detected the scheduling overrun error. This occurs when the Periodic list
does not complete before EOF. When a scheduling overrun error is detected, the Host
Controller increments the counter and sets the SchedulingOverrun field in the
HcInterruptStatus register.
The HcCommandStatus register is used by the Host Controller to receive commands
The SchedulingOverrunCount field indicates the number of frames with which the Host
HcCommandStatus Register
Mnemonic
－
SOC
OCR
31
15
30
14
Reserved
Scheduling
OverrunCount
Reserved
Ownership
ChangeRequest
29
13
Field name
28
12
27
11
TMPA901CM- 780
26
10
Reserved
These bits are incremented at each scheduling overrun error. It is
initialized to 00b and wraps around at 11b. This will be incremented
when a scheduling overrun is detected even if SchedulingOverrun in
HcInterruptStatus has already been set. This is used by HCD to
monitor any persistent scheduling problems.
This bit is set by the OS HCD to request a change of HC control. When
set, the HC will set the OwnershipChange field in HcInterruptStatus.
After the changeover, this bit is cleared and remains so until the next
request is made from the OS HCD.
25
Reserved
9
24
8
23
7
22
6
Address
Function
21
5
20
4
(0xF450_0000) + (0x0008)
OCR BLF
19
3
0
18
2
0
TMPA901CM
R/W
R/W
2010-07-29
CLF HCR
17
1
0
0
SOC
R/W
R
16
0
0
0