TMPA901CMXBG Toshiba, TMPA901CMXBG Datasheet - Page 170

• Manufacturer Part Number: TMPA901CMXBG
• Description: Microcontrollers (MCU) 32-bit RISC MCU 16kb ARM926EJ 16kb 200Mhz
• Manufacturer: Toshiba

Specifications of TMPA901CMXBG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): -
• Rom Type: ROMless
• Ram (kbytes): 32
• Number Of Pins: 177
• Package: BGA
• Vcc: 3V
• Tft Lcd Controller: Y
• Touchscreen Controller: Y
• Usb Host Fs With Phy: Y
• Usb Device Hs With Phy: Y
• Sd Host Controller: -
• Cmos Image Sensor Interface: -
• I2s: 1
• Ssp (ch) Spi: 1
• I2mc/sio (ch): 1
• Uart/sio (ch): 2
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 8
• 10-bit Ad Converter: 4
• 12-bit Da Converter: -
• 16-bit Timer / Counter: 6
• Real Time Clock: Y
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Low-power Modes: Y
• Lead Free Status / Rohs Status: Details

LCDDA
DMAC1
DMAC2
USB
output of LCDDA, USB, DMAC1, and
(Bus request from the bus matrix 3
3.10.3
CPU Inst (AHB0) bus request
LCDC (AHB2) bus request
CPU Data (AHB1) bus request
LCDC
CPU
Data
CPU
AHB
Inst
AHB3 bus request
Functions of MPMC0
Figure 3.10.1 is a simplified block diagram of MPMC0 circuits.
DMAC2)
(a)
Handling priority : ①→②→③→④→⑤
MPMC0
1. Bus matrix of AHB0, AHB1, AHB2 and AHB3 supports Round-Robin arbitration
Bus matrix
AHB3 interface M
scheme. The following diagram shows the priority of bus requests.
AHB0 interface M
AHB1 interface M
AHB2 interface M
Figure 3.10.1 MPMC0 Block Diagram
A dotted line is the point of handling end where bus is released.
①
③
④
②
AHB0
Handling
TMPA901CM-169
Round-Robin
AHB1
Handling
S
S
S
S
Bus matrix
AHB2
Handling
⑤
M
M
AHB3
Handling
S
S
APB S
M
AHB to APB
bridge
APB S
AHB0
Handling
DMC
SMC
M
S
TMPA901CM
2010-07-29
SDR
1chip
SRAM/NOR
2chips