TMPA901CMXBG Toshiba, TMPA901CMXBG Datasheet - Page 351

• Manufacturer Part Number: TMPA901CMXBG
• Description: Microcontrollers (MCU) 32-bit RISC MCU 16kb ARM926EJ 16kb 200Mhz
• Manufacturer: Toshiba

Specifications of TMPA901CMXBG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): -
• Rom Type: ROMless
• Ram (kbytes): 32
• Number Of Pins: 177
• Package: BGA
• Vcc: 3V
• Tft Lcd Controller: Y
• Touchscreen Controller: Y
• Usb Host Fs With Phy: Y
• Usb Device Hs With Phy: Y
• Sd Host Controller: -
• Cmos Image Sensor Interface: -
• I2s: 1
• Ssp (ch) Spi: 1
• I2mc/sio (ch): 1
• Uart/sio (ch): 2
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 8
• 10-bit Ad Converter: 4
• 12-bit Da Converter: -
• 16-bit Timer / Counter: 6
• Real Time Clock: Y
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Low-power Modes: Y
• Lead Free Status / Rohs Status: Details

[Description]
a. <SPS>
b. <WLEN>
c.
d. <STP2>
e. <EPS>
f.
<FEN>
When this bit is set to 1, even parity generation and checking are performed during
transmission and reception. This function checks whether the number of 1s contained in
the data bits and parity bit is even. When this bit is cleared to 0, odd parity check is
performed to check whether the number of 1s is odd. This bit has no effect when parity is
disabled by Parity Enable bit <PEN> being cleared to 0. Refer to Table 3.13.2 for the truth
table.
<PEN>
When this bit is set to 1, parity check and generation are enabled. Otherwise, parity is
disabled and no parity bit is added to data frames. Refer to Table 3.13.2 for the truth table
of SPS, EPS, and PEN bits.
When bits 1, 2, and 7 of the UARTxLCR_H register are set, the parity bit is transmitted
and checked as a 0. When bits 1 and 7 are set and bit 2 is 0, the parity bit is transmitted
and checked as a 1. When this bit is cleared, the stick parity is disabled. Refer to Table
3.13.2 for the truth table of SPS, EPS, and PEN bits.
This bit indicates the number of data bits transmitted or received in a frame.
When this bit is set to 1, transmit and receive FIFO buffers are enabled (FIFO mode).
When this bit is cleared to 0, the FIFOs are disabled (character mode) and they become
1-byte deep holding registers.
When this bit is set to 1, two stop bits are transmitted at the end of a frame. The receive
logic does not check for the second stop bit being received.
TMPA901CM- 350
TMPA901CM
2010-07-29