TMPA901CMXBG Toshiba, TMPA901CMXBG Datasheet - Page 231

• Manufacturer Part Number: TMPA901CMXBG
• Description: Microcontrollers (MCU) 32-bit RISC MCU 16kb ARM926EJ 16kb 200Mhz
• Manufacturer: Toshiba

Specifications of TMPA901CMXBG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): -
• Rom Type: ROMless
• Ram (kbytes): 32
• Number Of Pins: 177
• Package: BGA
• Vcc: 3V
• Tft Lcd Controller: Y
• Touchscreen Controller: Y
• Usb Host Fs With Phy: Y
• Usb Device Hs With Phy: Y
• Sd Host Controller: -
• Cmos Image Sensor Interface: -
• I2s: 1
• Ssp (ch) Spi: 1
• I2mc/sio (ch): 1
• Uart/sio (ch): 2
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 8
• 10-bit Ad Converter: 4
• 12-bit Da Converter: -
• 16-bit Timer / Counter: 6
• Real Time Clock: Y
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Low-power Modes: Y
• Lead Free Status / Rohs Status: Details

[31:3]
[2:0]
[Description]
Bit
a. <memc_cmd>
Note: The SDRAM can be shifted from ACTIVE to IDLE by either of the following two settings: dmc_direct_cmd_5<
2.
at this time varies depending on the immediately preceding command executed on the SDRAM.
If a Read or Write has been executed, the SDRAM will be shifted to ACTIVE. If AutoRefresh has
been executed, the SDRAM will be shifted to IDLE
transition from Pause to Config is effected by a Config command. Register settings must be
made during the Config state.
allowed. When a read or write is executed, the SDRAM will change from IDLE to ACTIVE.
Bank Precharge is executed, CKE will be driven “L” and the SDRAM will automatically
enter the Self-refresh state.
Self-refresh Exit command will be issued. The SDRAM then automatically exists the
Self-refresh state and enters the IDLE state.
Settings of this register can change the DMC state machine. If a previously issued
command for changing the states is being executed, a new command is issued after the
previous command is completed.
The following diagram shows DMC state transitions.
When the DMC state is Ready, a Pause command shifts the DMC to Pause. The SDRAM state
When the DMC exits the Reset state, it automatically enters the Config state. The state
When the DMC state is shifted to Ready, reads from and writes to the SDRAM are
When the DMC state is shifted from Pause to Low power by a Sleep command, after All
When the DMC state is shifted from Low power to Pause by a Wakeup command, a
dmc_memc_cmd_5 (DMC Memory Controller Command Register)
memory_cmd>0y00 = Prechargeall or 0y01 = Autorefresh
memc_cmd
Symbol
Bit
Reset
POR
config
External memory state transitions
WO
Type
TMPA901CM-230
Configure
Undefined
Reset
Value
Go
Pause
Sleep
Read as undefined. Write as zero.
Change the memory controller status:
0y000 = Go
0y010 = Wakeup
0y100 = Configure
Pause
Ready
Low
power
(Note).
Wakeup
Go
Description
0y001 = Sleep
0y011 = Pause
Address
(0xF431_0000) + (0x0004)
TMPA901CM
2010-07-29