TMPA901CMXBG Toshiba, TMPA901CMXBG Datasheet - Page 356

• Manufacturer Part Number: TMPA901CMXBG
• Description: Microcontrollers (MCU) 32-bit RISC MCU 16kb ARM926EJ 16kb 200Mhz
• Manufacturer: Toshiba

Specifications of TMPA901CMXBG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): -
• Rom Type: ROMless
• Ram (kbytes): 32
• Number Of Pins: 177
• Package: BGA
• Vcc: 3V
• Tft Lcd Controller: Y
• Touchscreen Controller: Y
• Usb Host Fs With Phy: Y
• Usb Device Hs With Phy: Y
• Sd Host Controller: -
• Cmos Image Sensor Interface: -
• I2s: 1
• Ssp (ch) Spi: 1
• I2mc/sio (ch): 1
• Uart/sio (ch): 2
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 8
• 10-bit Ad Converter: 4
• 12-bit Da Converter: -
• 16-bit Timer / Counter: 6
• Real Time Clock: Y
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Low-power Modes: Y
• Lead Free Status / Rohs Status: Details

16. UART0IFLS (UART0 Interrupt FIFO level select register)
17. UART1IFLS (UART1 Interrupt FIFO level select register)
[31:6]
[5:3]
[2:0]
[31:6]
[5:3]
[2:0]
[Description]
Bit
Bit
to define the FIFO level at which UARTTXINTR and UARTRXINTR are generated.
the level. For example, an interrupt is generated at a point when the third word has been
stored in the receive FIFO which contained two words.
The UARTxIFLS register is the interrupt FIFO level select register. This register is used
The interrupts are generated based on a transition through a level rather than based on
RXIFLSEL
TXIFLSEL
RXIFLSEL
TXIFLSEL
Symbol
Symbol
Bit
Bit
R/W
R/W
R/W
R/W
Type
Type
Undefined
0y010
0y010
Undefined
0y010
0y010
Reset
Reset
Value
Value
TMPA901CM- 355
Read as undefined. Write as zero.
Receive interrupt FIFO level select (1 word = 12 bits):
0y000: When the 2nd word has been stored in receive FIFO
0y001: When the 4th word has been stored in receive FIFO
0y010: When the 8th word has been stored in receive FIFO
0y011: When the 12th word has been stored in receive FIFO
0y100: When the 14th word has been stored in receive FIFO
0y101to 0y111: Reserved
Transmit FIFO level select (1 word = 8 bits):
0y000: When transmit FIFO has space for 2 words left
0y001: When transmit FIFO has space for 4 words left
0y010: When transmit FIFO has space for 8 words left
0y011: When transmit FIFO has space for 12 words left
0y100: When transmit FIFO has space for 14 words left
0y101 to 0y111: Reserved
Read as undefined. Write as zero.
Receive interrupt FIFO level select (1 word = 12 bits ):
0y000: When the 2nd word has been stored in receive FIFO
0y001: When the 4th word has been stored in receive FIFO
0y010: When the 8th word has been stored in receive FIFO
0y011: When the 12th word has been stored in receive FIFO
0y100: When the 14th word has been stored in receive FIFO
0y101 to 0y111: Reserved
Transmit interrupt FIFO level select ( 1 word = 8 bits):
0y000: When transmit FIFO has space for 2 words left
0y001: When transmit FIFO has space for 4 words left
0y010: When transmit FIFO has space for 8 words left
0y011: When transmit FIFO has space for 12 words left
0y100: When transmit FIFO has space for 14 words left
0y101 to 0y111: Reserved
Address
Address
Description
Description
(0xF200_1000) + 0x0034
(0xF200_0000) + (0x0034)
TMPA901CM
2010-07-29