TMPA901CMXBG Toshiba, TMPA901CMXBG Datasheet - Page 408

• Manufacturer Part Number: TMPA901CMXBG
• Description: Microcontrollers (MCU) 32-bit RISC MCU 16kb ARM926EJ 16kb 200Mhz
• Manufacturer: Toshiba

Specifications of TMPA901CMXBG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): -
• Rom Type: ROMless
• Ram (kbytes): 32
• Number Of Pins: 177
• Package: BGA
• Vcc: 3V
• Tft Lcd Controller: Y
• Touchscreen Controller: Y
• Usb Host Fs With Phy: Y
• Usb Device Hs With Phy: Y
• Sd Host Controller: -
• Cmos Image Sensor Interface: -
• I2s: 1
• Ssp (ch) Spi: 1
• I2mc/sio (ch): 1
• Uart/sio (ch): 2
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 8
• 10-bit Ad Converter: 4
• 12-bit Da Converter: -
• 16-bit Timer / Counter: 6
• Real Time Clock: Y
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Low-power Modes: Y
• Lead Free Status / Rohs Status: Details

I2C0SR<LRB>
I2CINT0 interrupt request
3.14.6.13 Last Received Bit Monitor
3.14.6.14 Setting the Slave address and Address Recognition Mode
SCL (bus)
SDA (bus)
1. When I
recognized and bits immediately following a start condition are handled as data.
To use I
To use the free data format in which slave addresses are not recognized, set I2C0AR<ALS> to
I2C0SR<LRB> immediately after generation of an I2CINT0 interrupt request.
I2C0SR<LRB> stores the SDA line value captured on every rising edge of the SCL line.
When acknowledge operation is enabled, the acknowledge signal is read from
2
C in I
2
C is used with the free data format, the slave address and direction bit are not
Figure 3.14.22 Changes in the last received bit monitor
2
C bus mode, clear I2C0AR<ALS> to 0 and set a slave address in I2C0AR<SA>.
D7
1
D7
D6
2
D6
TMPA901CM- 407
D5
3
D5
D4
4
D4
D3
5
D3
D2
6
D2
D1
7
D1
D0
8
D0
ACK
9
ACK
TMPA901CM
2010-07-29