TMPA901CMXBG Toshiba, TMPA901CMXBG Datasheet - Page 168

• Manufacturer Part Number: TMPA901CMXBG
• Description: Microcontrollers (MCU) 32-bit RISC MCU 16kb ARM926EJ 16kb 200Mhz
• Manufacturer: Toshiba

Specifications of TMPA901CMXBG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): -
• Rom Type: ROMless
• Ram (kbytes): 32
• Number Of Pins: 177
• Package: BGA
• Vcc: 3V
• Tft Lcd Controller: Y
• Touchscreen Controller: Y
• Usb Host Fs With Phy: Y
• Usb Device Hs With Phy: Y
• Sd Host Controller: -
• Cmos Image Sensor Interface: -
• I2s: 1
• Ssp (ch) Spi: 1
• I2mc/sio (ch): 1
• Uart/sio (ch): 2
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 8
• 10-bit Ad Converter: 4
• 12-bit Da Converter: -
• 16-bit Timer / Counter: 6
• Real Time Clock: Y
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Low-power Modes: Y
• Lead Free Status / Rohs Status: Details

smc_timeout
two Access requests of DMC and SMC are generated, EBI keeps the one Access request wait, when
the other is accessing.
generated continuously, EBI manage the overlapped time, also it has a “Timeout counter”; the bus
is released forcibly.
priority of the DMC becomes..
register.
register are Low-order 8bits only. The most significant bit (bit 7) of effective bits controls
High-order 3bits of the 10 bit counter.
Register
Name
EBI shifts the bus according to the access request from memory controller (DMC and SMC). If
To avoid the one Access request is made to wait for a long time when one Access request is
In the TMPA901CM, the higher the access speed and the frequency become, the higher the
Therefore, it has function to prioritize DMC request by setting Timeout cycle of SMC side to
The smc_timeout cycle is controlled by a 10 bit counter, however, the effective bits in control
Note: “0x00000000” cannot be set. “0x00000001 to 0x000000FF” only is effective.
Note: To avoid an underflow in LCDC when setting DMC memory (SDRAM) to VRAM of LCDC,It is recommended to
SMC timeout cycle setting register
smc_timeout register
set this register to 0y01.Please use this function together with the QOS function (refer to “DMC“ section)
bit31 to bit8
DMC time out cycle
0x0050
1024 clocks (Fixed)
Address
(base+)
bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
Table 3.10.2 Timeout for EBI
Type
R/W
TMPA901CM-167
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
Reset value
0x000000FF
TIMEOUT Counter
to 1024 clocks (configurable with register)
SMC Timeout Register
SMC time out cycle
Description
Base address
TMPA901CM
0xF00A_0000
2010-07-29