TMPA901CMXBG Toshiba, TMPA901CMXBG Datasheet - Page 354

• Manufacturer Part Number: TMPA901CMXBG
• Description: Microcontrollers (MCU) 32-bit RISC MCU 16kb ARM926EJ 16kb 200Mhz
• Manufacturer: Toshiba

Specifications of TMPA901CMXBG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): -
• Rom Type: ROMless
• Ram (kbytes): 32
• Number Of Pins: 177
• Package: BGA
• Vcc: 3V
• Tft Lcd Controller: Y
• Touchscreen Controller: Y
• Usb Host Fs With Phy: Y
• Usb Device Hs With Phy: Y
• Sd Host Controller: -
• Cmos Image Sensor Interface: -
• I2s: 1
• Ssp (ch) Spi: 1
• I2mc/sio (ch): 1
• Uart/sio (ch): 2
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 8
• 10-bit Ad Converter: 4
• 12-bit Da Converter: -
• 16-bit Timer / Counter: 6
• Real Time Clock: Y
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Low-power Modes: Y
• Lead Free Status / Rohs Status: Details

15. UART1CR (UART1 control register)
[31:16]
[15]
[14:10]
[9]
[8]
[7]
[6:1]
[0]
[Description]
a. <CTSEN>
b. <RTSEN>
c.
d. <DTR>
e. <RXE>
f.
Bit
When this bit is set to 1, CTS hardware flow control is enabled. Data is transmitted only
after the UxCTSn signal has been asserted.
When this bit is set to 1, RTS hardware flow control is enabled. Data is transmitted only
when there is an empty space in the receive FIFO.
<RTS>
This bit is the UART Request To Send (UxRTSn) modem status output signal. When this
bit is set to 1, the output is 0.
This bit is the UART Data Transmit Ready (UxDTRn) modem status output signal. When
this bit is set to 1, the output is 0.
When this bit is set to 1, the receive circuit of the UART is enabled. Data reception occurs
for either UART function or SIR function according to the setting of <SIREN>. When the
UART is disabled in the middle of receive operation, it completes current reception and
the subsequent receptions are disabled.
<TXE>
When this bit is set to 1, the transmit circuit of the UART is enabled. Data transmission
occurs for either UART function or SIR function according to the setting of <SIREN>.
When the UART is disabled in the middle of transmit operation, it completes the current
transmission before stopping.
CTSEN
RXE
TXE
Reserved
Reserved
UARTEN
Symbol
Bit
R/W
R/W
R/W
R/W
R/W
Type
TMPA901CM- 353
Undefined
0y0
Undefined
0y1
0y1
0y0
Undefined
0y0
Reset
Value
Read as undefined. Write as zero.
CTS hardware flow control enable
0y0: Disable
0y1: Enable
Read as undefined. Write as zero.
UART receive enable
0y0: Disable
0y1: Enable
UART transmit enable
0y0: Disable
0y1: Enable
Write as zero.
Read as undefined. Write as zero.
UART enable
0y0: Disable
0y1: Enable
Address
Description
(0xF200_1000) + (0x0030)
TMPA901CM
2010-07-29