TMPA901CMXBG Toshiba, TMPA901CMXBG Datasheet - Page 60

• Manufacturer Part Number: TMPA901CMXBG
• Description: Microcontrollers (MCU) 32-bit RISC MCU 16kb ARM926EJ 16kb 200Mhz
• Manufacturer: Toshiba

Specifications of TMPA901CMXBG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): -
• Rom Type: ROMless
• Ram (kbytes): 32
• Number Of Pins: 177
• Package: BGA
• Vcc: 3V
• Tft Lcd Controller: Y
• Touchscreen Controller: Y
• Usb Host Fs With Phy: Y
• Usb Device Hs With Phy: Y
• Sd Host Controller: -
• Cmos Image Sensor Interface: -
• I2s: 1
• Ssp (ch) Spi: 1
• I2mc/sio (ch): 1
• Uart/sio (ch): 2
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 8
• 10-bit Ad Converter: 4
• 12-bit Da Converter: -
• 16-bit Timer / Counter: 6
• Real Time Clock: Y
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Low-power Modes: Y
• Lead Free Status / Rohs Status: Details

9. CLKCR5 (Clock Control Register-5)
[31:7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
[Description]
a. < USBH_CLKEN >
b. <SEL_TIM45>
c. <SEL_TIM23>
d. <SEL_TIM01>
Bit
Clock selection for USB Host controller
0y0: Disable
0y1: Enable
Selects the prescaler clock for Timer45.
0y0: fs (32.768 kHz) clock
0y1: f
Selects the prescaler clock for Timer23.
0y0: fs (32.768 kHz) clock
0y1: f
Selects the prescaler clock for Timer01.
0y0: fs (32.768 kHz) clock
0y1: f
Reserved
Reserved
SEL_TIM45
SEL_TIM23
SEL_TIM01
USBH_CLKEN
If the user desires to change a setting of the clock for USB Host, the user must disable
the output of the clock first.
PCLK
PCLK
PCLK
Symbol
Bit
/2
/2
/2
R/W
R/W
R/W
R/W
R/W
R/W
Type
TMPA901CM- 59
Undefined
0y1
Undefined
0y1
0y1
0y1
0y1
0y1
Reset
Value
Read as undefined. Write as zero.
Read as undefined. Write as one.
Read as undefined. Write as zero.
Write as one
Selection of a prescaler clock for Timer45
0y0: fs (32.768 kHz) clock
0y1: f
Selection of a prescaler for Timer23
0y0: fs (32.768 kHz) clock
0y1: f
Selection of a prescaler for Timer01
0y0: fs (32.768 kHz) clock
0y1: f
Clock selection for USB HOST controller
0y0 : disable
0y1 : enable
PCLK
PCLK
PCLK
/2
/2
/2
Address
Description
(0xF005_0000)
TMPA901CM
2010-07-29
(0x0054)