TMPA901CMXBG Toshiba, TMPA901CMXBG Datasheet - Page 794

• Manufacturer Part Number: TMPA901CMXBG
• Description: Microcontrollers (MCU) 32-bit RISC MCU 16kb ARM926EJ 16kb 200Mhz
• Manufacturer: Toshiba

Specifications of TMPA901CMXBG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): -
• Rom Type: ROMless
• Ram (kbytes): 32
• Number Of Pins: 177
• Package: BGA
• Vcc: 3V
• Tft Lcd Controller: Y
• Touchscreen Controller: Y
• Usb Host Fs With Phy: Y
• Usb Device Hs With Phy: Y
• Sd Host Controller: -
• Cmos Image Sensor Interface: -
• I2s: 1
• Ssp (ch) Spi: 1
• I2mc/sio (ch): 1
• Uart/sio (ch): 2
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 8
• 10-bit Ad Converter: 4
• 12-bit Da Converter: -
• 16-bit Timer / Counter: 6
• Real Time Clock: Y
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Low-power Modes: Y
• Lead Free Status / Rohs Status: Details

Read/Write
(HCD)
Read/Write
(HC)
Read/Write
(HCD)
Read/Write
(HC)
bit Symbol
Reset state
bit Symbol
Reset state
[31]
[30:16]
[15:14]
[13:0]
Bit
14. HcFmInterval Register
in a Frame, (i.e., between two consecutive SOFs), and a 15-bit value indicating the Full
Speed maximum packet size that the Host Controller may transmit or receive without
causing scheduling overrun. The Host Controller Driver may carry out minor adjustment
on the FrameInterval by writing a new value over the present one at each SOF. This
provides the programmability required for the Host Controller to synchronize with an
external clocking resource and to adjust any unfixed local clock offset.
The HcFmInterval register contains a 14-bit value which indicates the bit time interval
Mnemonic
FIT
FSMPS
－
FI
R/W
FIT
31
15
Reserved
R
0
30
14
FrameInterval
Toggle
FSLargestData
Packet
Reserved
FrameInterval
29
13
1
Field name
28
12
0
27
11
TMPA901CM- 793
1
26
10
1
HCD toggles this bit each time it loads a new value to FrameInterval.
This field specifies a value which is loaded into the Largest Data
Packet Counter at the beginning of each frame. The counter value
represents the largest amount of data in bits which can be sent or
received by the HC in a single transaction at any given time without
causing a scheduling overrun. The field value is calculated by HCD.
This field specifies the interval between two consecutive SOFs in bit
times. The nominal value is set to be 11,999. HCD should store the
current value of this field before resetting the HC. By setting the
HostControllerReset field of HcCommandStatus the HC resets this
field to its nominal value. HCD may choose to restore the stored value
upon the completion of the Reset sequence.
25
9
1
24
8
0
FSMPS
R/W
TBD
23
R
7
1
R/W
FI
R
22
6
1
Address
Function
21
5
0
20
4
1
(0xF450_0000) + (0x0034)
19
3
1
18
2
1
TMPA901CM
2010-07-29
17
1
1
16
0
1