TMPA901CMXBG Toshiba, TMPA901CMXBG Datasheet - Page 39

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TMPA901CMXBG

Manufacturer Part Number
TMPA901CMXBG
Description
Microcontrollers (MCU) 32-bit RISC MCU 16kb ARM926EJ 16kb 200Mhz
Manufacturer
Toshiba
Datasheet

Specifications of TMPA901CMXBG

Product Summaries
Summary
Lead Free
Yes
Rohs Compatible Product(s)
Available
Rom (kbytes)
-
Rom Type
ROMless
Ram (kbytes)
32
Number Of Pins
177
Package
BGA
Vcc
3V
Tft Lcd Controller
Y
Touchscreen Controller
Y
Usb Host Fs With Phy
Y
Usb Device Hs With Phy
Y
Sd Host Controller
-
Cmos Image Sensor Interface
-
I2s
1
Ssp (ch) Spi
1
I2mc/sio (ch)
1
Uart/sio (ch)
2
External Bus Interface
Y
Cs/wait Controller (ch)
4
Dma Controller
8
10-bit Ad Converter
4
12-bit Da Converter
-
16-bit Timer / Counter
6
Real Time Clock
Y
Watchdog Timer
Y
Osc Freq Detect
Y
Low-power Modes
Y
Lead Free Status / Rohs Status
 Details

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
TMPA901CMXBG
Manufacturer:
Toshiba
Quantity:
10 000
1) The PR2 pin serves as an I/O pin. However, the PR2 pin does not support the capture function
2) The JTAG circuit can be released from the reset state by either of the following two methods:
processor.
Notes
(3) BYPASS instruction
(4) CLAMP instruction
(5) HIGHZ instruction
This section describes the cautions of the JTAG boundary-scan operations specific to the
by using SAMPLE/PRELOAD instructions because the BSR is connected to the pin.
register provides the shortest serial path that bypasses the IC (between JTDI and JTDO)
when the test does not require control or monitoring of the IC. The BYPASS instruction
does not cause interference in the normal operation of the on-chip system logic. Figure
3.2.10 shows the data flow through the bypass register when the BYPASS instruction is
selected.
HIGHZ instruction is executed, it places the 3-state output pins in the high-impedance
state.
・ Assert TRSTn, initialize the JTAG circuit, and then deassert TRSTn.
・ Supply the TCK signal for 5 or more clock pulses to TCK while pulling the TMS pin
according to the PRELOAD instruction, and execute Bypass operation.
The CLAMP instruction outputs the value that boundary scan register is programmed
The CLAMP instruction selects the bypass register between TDI and TDO.
The HIGHZ instruction disables the output of the internal logical circuits. When the
The HIGHZ instruction also selects the bypass register between TDI and TDO.
This instruction targets the bypass register between JTDI and JTDO. The bypass
High.
Figure 3.2.10 Test Data Flow when the BYPASS Instruction is Selected
TDI
TMPA901CM- 38
Bypass register
1 bit
TDO
TMPA901CM
2010-07-29

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