TMPA901CMXBG Toshiba, TMPA901CMXBG Datasheet - Page 237

• Manufacturer Part Number: TMPA901CMXBG
• Description: Microcontrollers (MCU) 32-bit RISC MCU 16kb ARM926EJ 16kb 200Mhz
• Manufacturer: Toshiba

Specifications of TMPA901CMXBG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): -
• Rom Type: ROMless
• Ram (kbytes): 32
• Number Of Pins: 177
• Package: BGA
• Vcc: 3V
• Tft Lcd Controller: Y
• Touchscreen Controller: Y
• Usb Host Fs With Phy: Y
• Usb Device Hs With Phy: Y
• Sd Host Controller: -
• Cmos Image Sensor Interface: -
• I2s: 1
• Ssp (ch) Spi: 1
• I2mc/sio (ch): 1
• Uart/sio (ch): 2
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 8
• 10-bit Ad Converter: 4
• 12-bit Da Converter: -
• 16-bit Timer / Counter: 6
• Real Time Clock: Y
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Low-power Modes: Y
• Lead Free Status / Rohs Status: Details

[31:4]
[3:1]
[0]
[Description]
Bit
a. <cas_latency>
b. <cas_half_cycle>
Note:
6.
CAS latency setting (number of memory clocks): 0y000 to 0y111
CAS latency offset setting:
0y0 = 0 offset
0y1 = Half-cycle offset
Use dmc_cas_latency_5 to configure cas latency of memory controler,
The setting of cas latency(CL) is different from SDR_SDRAM.
The CL setting value of memory controler is 1 smaller than the CL setting value of
DDR_SDRAM memory.
Example:
dmc_cas_latency_5 ← 0x00000004 (set memory controller CL = 2)
dmc_direct_cmd_5 ← 0x00080033
dmc_cas_latency_5 (DMC CAS Latency Register)
cas_latency
cas_half_cycle
Symbol
Bit
R/W
R/W
Type
TMPA901CM-236
Undefined
0y11
0y0
Reset
Value
(set DDR SDRAM memory CL = 3)
Read as undefined. Write as zero.
CAS latency setting (number of memory clocks)
0y000 to 0y111
set CAS latency offset
0y0 = 0 offset
0y1 = Half cycle offset
Address
Description
(0xF431_0000) + (0x0014)
TMPA901CM
2010-07-29