TMPA901CMXBG Toshiba, TMPA901CMXBG Datasheet - Page 379

• Manufacturer Part Number: TMPA901CMXBG
• Description: Microcontrollers (MCU) 32-bit RISC MCU 16kb ARM926EJ 16kb 200Mhz
• Manufacturer: Toshiba

Specifications of TMPA901CMXBG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): -
• Rom Type: ROMless
• Ram (kbytes): 32
• Number Of Pins: 177
• Package: BGA
• Vcc: 3V
• Tft Lcd Controller: Y
• Touchscreen Controller: Y
• Usb Host Fs With Phy: Y
• Usb Device Hs With Phy: Y
• Sd Host Controller: -
• Cmos Image Sensor Interface: -
• I2s: 1
• Ssp (ch) Spi: 1
• I2mc/sio (ch): 1
• Uart/sio (ch): 2
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 8
• 10-bit Ad Converter: 4
• 12-bit Da Converter: -
• 16-bit Timer / Counter: 6
• Real Time Clock: Y
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Low-power Modes: Y
• Lead Free Status / Rohs Status: Details

5. Restart Procedure
Note:
terminating data transfer to the slave device. The restart procedure is explained below.
I2C0CR2<PIN>. The I2C0DA line remains high and the I2C0CL line is released.
released.
pulled low by another device.
explained earlier in “2. Start Condition and Slave Address Generation”.
software, a wait period of 4.7 s or longer in the case of standard mode and 0.6 s or longer
in the case of fast mode.
CHK _ BB:
CHK _ LRB:
Then, check I2C0SR<LRB> until it becomes 1 to make sure that the I2C0CL line is not
Programming example: Generating a restart condition
Restart is used to change the direction of data transfer without the master device
First, write 0 to I2C0CR2<MST>, I2C0CR2<TRX>, I2C0CR2<BB> and 1 to
Since this is not a stop condition, the bus remains busy for other devices.
After making sure that the bus is free by these steps, generate a start condition as
In order to satisfy the setup time requirement for restart, it is necessary to insert, by
Next, check I2C0SR<BB> until it is cleared to 0 to make sure that the I2C0CL line is
When the master device is operating as a receiver, it is necessary to terminate the data transfer from the
slave transmitter before the restart procedure can be started. To do so, the master device makes the slave
device receive the negative acknowledge signal (high). Therefore, I2C0SR<LRB> is set to 1 before the
restart procedure is started. The SCL line level cannot be determined by checking I2C0SR<LRB>
the restart procedure. The state of the I2C0CL line shold be checked by reading the port.
(I2C0CR2) ←
r1
AND
CMP
BNE
r1
AND
CMP
BNE
(I2C0CR2) ←
←
←
TMPA901CM- 378
0x18
r1, #0x20
r1, #0x00
r1, #0x01
(I2C0SR)
CHK _ BB
(I2C0SR)
r1, #0x01
CHK _ LRB
･
･
0xF8
; Set I2C0CR2<MST>, <TRX>,<BB> to 0 and
I2C0CR2<PIN> to 1.
; Wait until I2C0SR<BB> is cleared to 0.
; Wait until I2C0SR<LRB> becomes 1.
; Wait by software
; Set I2C0CR2<MST>, <TRX>, <BB>, <PIN> to 1.
TMPA901CM
2010-07-29
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