TMPA901CMXBG Toshiba, TMPA901CMXBG Datasheet - Page 762

• Manufacturer Part Number: TMPA901CMXBG
• Description: Microcontrollers (MCU) 32-bit RISC MCU 16kb ARM926EJ 16kb 200Mhz
• Manufacturer: Toshiba

Specifications of TMPA901CMXBG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): -
• Rom Type: ROMless
• Ram (kbytes): 32
• Number Of Pins: 177
• Package: BGA
• Vcc: 3V
• Tft Lcd Controller: Y
• Touchscreen Controller: Y
• Usb Host Fs With Phy: Y
• Usb Device Hs With Phy: Y
• Sd Host Controller: -
• Cmos Image Sensor Interface: -
• I2s: 1
• Ssp (ch) Spi: 1
• I2mc/sio (ch): 1
• Uart/sio (ch): 2
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 8
• 10-bit Ad Converter: 4
• 12-bit Da Converter: -
• 16-bit Timer / Counter: 6
• Real Time Clock: Y
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Low-power Modes: Y
• Lead Free Status / Rohs Status: Details

[31:5]
[4]
[3:2]
[1]
[0]
[31:1]
[0]
[Description]
[Description]
12. PMCDRV register
13. DMCCKECTL register
SDRAM has been set to self-refresh mode before entering the Power Cut Mode, the self-refresh
mode will be cleared when the DMCCKE pin is initialized to the “H” level after wake-up from
the Power Cut Mode. To avoid this situation, it is possible only for the DMCCKE pin, which
controls SDRAM, to specify different pin levels after a system reset and after wake-up from
the Power Cut Mode. The DMCCKE pin level after wake-up from the Power Cut Mode can be
set in the relevant PMC register.
Bit
Bit
After a system reset, the DMCCKE pin is always initialized to the “H” level. Therefore, if
a. < DRV_LCD, DRV_MEM[1:0]>
a. <DMCCKEHLD >
These bits can be used to change the drive capability of ports related to LCD and
memory according to the voltage range to be used.
DRV_LCD
DRV_MEM1
DRV_MEM0
DMCCKEHLD
Bit Symbol
Bit Symbol
After a system reset
After wake-up from Power
Cut Mode
R/W
R/W
R/W
R/W
Type
Type
TMPA901CM- 761
Undefined
0y1
Undefined
0y0
0y1
Undefined
0y0
Reset
Reset
Value
Value
“H” level
To set the DMCCKE pin to “L” level:
DMCCKECTL<DMCCKEHLD>= 0y1
BSJOE<BSJOE6>= 0y1
BSJDATA<BSJDATA6>= 0y0
DMCCKE pin status
Undefined
hold eve data
Undefined
hold eve data
hold eve data
Undefined
hold eve data
Hot Reset
Hot Reset
Value
Value
Read as undefined. Write as zero.
LCDC relation port drive power
Read as undefined. Write as zero.
memory relation port drive power
Read as undefined. Write as zero.
output selection of SJ6
Address
Address
0y0: 12 mA (1.8 V to 3.0 V)
0y1: 6 mA (3.0 V to 3.6 V)
0y00: Reserved
0y01: 1/2 (3.3 V ±0.3 V)
0y10: Reserved
0y11: 1/1 (1.8 V ±0.1 V)
0y0: DMCCKE
0y1: PMC register setting
(0xF002_0000) + (0x0260)
(0xF002_0000) + (0x0280)
Description
Description
TMPA901CM
2010-07-29