TMPA901CMXBG Toshiba, TMPA901CMXBG Datasheet - Page 405

• Manufacturer Part Number: TMPA901CMXBG
• Description: Microcontrollers (MCU) 32-bit RISC MCU 16kb ARM926EJ 16kb 200Mhz
• Manufacturer: Toshiba

Specifications of TMPA901CMXBG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): -
• Rom Type: ROMless
• Ram (kbytes): 32
• Number Of Pins: 177
• Package: BGA
• Vcc: 3V
• Tft Lcd Controller: Y
• Touchscreen Controller: Y
• Usb Host Fs With Phy: Y
• Usb Device Hs With Phy: Y
• Sd Host Controller: -
• Cmos Image Sensor Interface: -
• I2s: 1
• Ssp (ch) Spi: 1
• I2mc/sio (ch): 1
• Uart/sio (ch): 2
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 8
• 10-bit Ad Converter: 4
• 12-bit Da Converter: -
• 16-bit Timer / Counter: 6
• Real Time Clock: Y
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Low-power Modes: Y
• Lead Free Status / Rohs Status: Details

SCL (line)
Internal SDA output
(Master A)
Internal SDA output
(Master B)
SDA line
3.14.6.10 Arbitration Lost Detection Monitor
feature must be implemented to ensure the integrity of transferred data.
devices exist on the bus simultaneously.
and Master A outputs 0. This causes the SDA line to be pulled low by Master A since the
SDA line is driven by the wired AND method.
i.e., the data from Master A.
lost”. Master B that lost arbitration must release I2C0DA and I2C0CL so that Master A can
use the bus without any hindrance. If more than one master outputs identical data on the
first word, the arbitration procedure is continued on the second word.
rising edge of the SCL line. If the two levels do not match, arbitration lost is determined
and I2C0SR<AL> is set to 1.
thereby selecting slave receiver mode. Thus, after I2C0SR<AL> is set to 1, Master B stops
clock output. After the data transfer on the bus is completed, I2C0SR<PIN> is cleared to 0
and I2C0CL is pulled low.
is written to I2C0CR2.
Since the I
The I
The following shows an example of the bus arbitration procedure when two master
Master A and Master B output the same data until point “a”, where Master B outputs 1
When the SCL line rises at point “b”, the slave device captures the data on the SDA line,
At this time, the data output from Master B becomes invalid. This is called “arbitration
Master B compares the level of I2C0DA with the level of the SDA line on the bus on the
When I2C0SR<AL> is set to 1, I2C0SR<MST> and I2C0SR<TRX> are cleared to 0,
I2C0SR<AL> is cleared to 0 when data is written to or read from I2C0DBR or when data
2
C bus uses data on the SDA line for bus arbitration.
2
C bus allows multiple masters to exist simultaneously, the bus arbitration
Figure 3.14.18 Arbitration lost
TMPA901CM- 404
a
b
Arbitration lost
Internal SDA output = 1
TMPA901CM
2010-07-29