TMPA901CMXBG Toshiba, TMPA901CMXBG Datasheet - Page 584

• Manufacturer Part Number: TMPA901CMXBG
• Description: Microcontrollers (MCU) 32-bit RISC MCU 16kb ARM926EJ 16kb 200Mhz
• Manufacturer: Toshiba

Specifications of TMPA901CMXBG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): -
• Rom Type: ROMless
• Ram (kbytes): 32
• Number Of Pins: 177
• Package: BGA
• Vcc: 3V
• Tft Lcd Controller: Y
• Touchscreen Controller: Y
• Usb Host Fs With Phy: Y
• Usb Device Hs With Phy: Y
• Sd Host Controller: -
• Cmos Image Sensor Interface: -
• I2s: 1
• Ssp (ch) Spi: 1
• I2mc/sio (ch): 1
• Uart/sio (ch): 2
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 8
• 10-bit Ad Converter: 4
• 12-bit Da Converter: -
• 16-bit Timer / Counter: 6
• Real Time Clock: Y
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Low-power Modes: Y
• Lead Free Status / Rohs Status: Details

[31:14]
[13:12]
[11:9]
[8]
[7:3]
[2]
[1]
[0]
[Description]
Bit
a. <I2SRx_RLCH_CUT>
b. <I2SRx_BITCNV>
2.
0y00: Stereo setting (both channel output)
0y01: Monaural setting (Right-side channel output)
0y10: Monaural setting (Left-side channel output)
0y11: Don’t setting
Specifies whether to invert the MSB (sign bit).
0y0: Not inverted
0y1: Inverted
Stereo/monaural (Right-side channel output, left-side channel output) output setting.
I2SRCON (Rx Control Register)
I2SRx_RCH_CUT
I2SRx_BITCNV
I2SRx_MSBINV
I2SRx_WSINV
I2SRx_DELAYOFF
Bit Symbol
R/W
R/W
R/W
R/W
R/W
Type
TMPA901CM- 583
Undefined
0y00
Undefined
0y0
Undefined
0y0
0y0
0y0
Reset
Value
Stereo/Monaural output setting
0y00: Stereo setting (both channel output)
0y01: Monaural setting (Right-side channel
0y10: Monaural setting (Left-side channel
0y11:Don’t setting
Read as undefined. Write as zero.
Read as undefined. Write as zero.
MSB (sign bit) inversion
0y0: Not inverted
0y1: Inverted
Read as undefined. Write as zero.
LSB/MSB first 0y0: MSB first
0y1: LSB first
WS channel definition inversion
0y0: WS= 1 (RCH), WS= 0 (LCH)
0y1: WS channel definition inverted
Relationship between Data output timing and
WS
0y0: Delay of 1CLOCK from WS
0y1: No delay from WS
WS= 0 (RCH), WS= 1 (LCH)
output)
output)
Address
Description
(0xF204_0000) + (0x0020)
TMPA901CM
2010-07-29