TMPA901CMXBG Toshiba, TMPA901CMXBG Datasheet - Page 34

• Manufacturer Part Number: TMPA901CMXBG
• Description: Microcontrollers (MCU) 32-bit RISC MCU 16kb ARM926EJ 16kb 200Mhz
• Manufacturer: Toshiba

Specifications of TMPA901CMXBG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): -
• Rom Type: ROMless
• Ram (kbytes): 32
• Number Of Pins: 177
• Package: BGA
• Vcc: 3V
• Tft Lcd Controller: Y
• Touchscreen Controller: Y
• Usb Host Fs With Phy: Y
• Usb Device Hs With Phy: Y
• Sd Host Controller: -
• Cmos Image Sensor Interface: -
• I2s: 1
• Ssp (ch) Spi: 1
• I2mc/sio (ch): 1
• Uart/sio (ch): 2
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 8
• 10-bit Ad Converter: 4
• 12-bit Da Converter: -
• 16-bit Timer / Counter: 6
• Real Time Clock: Y
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Low-power Modes: Y
• Lead Free Status / Rohs Status: Details

Shift-DR
Exit 1-DR
Pause-DR
Exit 2-DR
Update-DR
Capture-IR
Shift-IR
In this controller state, the test data register connected between TDI and TDO shifts
data out serially.
When the TAP controller is in this state, then it remains in the Shift-DR state if TMS is
held low, or moves to the Exit 1-DR state if TMS is held high.
This is a temporary controller state.
If TMS is held low when the TAP controller is in this state, the controller moves to the
Pause-DR state. If TMS is held high, the controller moves to the Update-DR state.
This state allows the shifting of the data register selected by the instruction register to
be temporarily suspended. Both the instruction register and the data register retain
their current states.
When the TAP controller is in this state, then it remains in the Pause-DR state if TMS
is held low, or moves to the Exit 2-DR state.
This is a temporary controller state.
When the TAP controller is in this state, it returns to the Shift-DR state if TMS is held
low, or moves on to the Update-DR state if TMS is held high.
In this state, data is latched, on the rising edge of TCK, onto the parallel outputs of the
data registers from the shift register path. The data held at the parallel output does
not change while data is shifted in the associated shift register path.
When the TAP controller is in this state, it moves to either the Run-Test/Idle state if
TMS is held low, or the Select-DR-Scan state if TMS is held high.
In this state, data is parallel-loaded into the instruction register. The data to be loaded
is 0y0001. The Capture-IR state is used for testing the instruction register. Faults in
the instruction register, if any, may be detected by shifting out the loaded data.
When the TAP controller is in this state, it moves to either the Shift-IR state if TMS is
held low, or the Exit 1-IR state if TMS is high.
In this state, the instruction register is connected between TDI and TDO and shifts the
captured data toward its serial output on the rising edge of TCK.
When the TAP controller is in this state, it remains in the Shift-IR state if TMS is low,
or moves to the Exit 1-IR state if TMS is high.
TMPA901CM- 33
TMPA901CM
2010-07-29