TMPA901CMXBG Toshiba, TMPA901CMXBG Datasheet - Page 570

• Manufacturer Part Number: TMPA901CMXBG
• Description: Microcontrollers (MCU) 32-bit RISC MCU 16kb ARM926EJ 16kb 200Mhz
• Manufacturer: Toshiba

Specifications of TMPA901CMXBG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): -
• Rom Type: ROMless
• Ram (kbytes): 32
• Number Of Pins: 177
• Package: BGA
• Vcc: 3V
• Tft Lcd Controller: Y
• Touchscreen Controller: Y
• Usb Host Fs With Phy: Y
• Usb Device Hs With Phy: Y
• Sd Host Controller: -
• Cmos Image Sensor Interface: -
• I2s: 1
• Ssp (ch) Spi: 1
• I2mc/sio (ch): 1
• Uart/sio (ch): 2
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 8
• 10-bit Ad Converter: 4
• 12-bit Da Converter: -
• 16-bit Timer / Counter: 6
• Real Time Clock: Y
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Low-power Modes: Y
• Lead Free Status / Rohs Status: Details

(2)
(UDC2-Input)
suspend_x
(UDC2-Output)
SuspendM
(PHY-Input)
(PHY-Output)
DDP/DDM
wakeup
CLK
Resume Operation by the Device (Remote Wakeup)
T0: suspend_x output of UDC2 = “L”
T1: Remote wakeup start enable (more than 2 ms after T0)
T2: Wakeup input to UDC2 = “H” (after T1)
T3: Start of device resume (Depends on the PHY specifications.)
T4: End of host resume (more than 20 ms after T3)
The device can be brought out of the suspend state by using the wakeup input of UDC2.
This is called remote wakeup. Note that the USB specification prohibits remote wakeup
for 5 ms after start of the suspend state. The wakeup signal should be set to “H” a
minimum of 2 ms after T0 as 3 ms have already elapsed from the start of suspend
operation to T0.
Set the wakeup signal to “H”. No timing requirements are specified for this operation. At
this point, UDC2 sets suspend_x to “H”. (Even if the clock input to UDC2 is stopped,
suspend_x becomes “H”.) Because UDC2 requires the clock input to start resume
operation (“FS-K”), the SuspendM (UTMI) input to USB 2.0 PHY should be disabled.
Then, keep wakeup at “H” until clock supply is resumed.
When the clock input from PHY to UDC2 is resumed, UDC2 starts the device resume
(“FS2-K”). The device resume period is approximately 2 ms. After confirming the device
resume, the host starts the host resume operation.
The host resume operation (“FS-K”) lasts for more than 20 ms, and completes after “SE0”.
UDC2 resumes operating at the same speed (HS/FS) as before the suspend state was
entered.
time
T0
Figure 3.16.32 Remote wakeup operation timing
FS Idle (“J”)
T1
TMPA901CM- 569
CLK-Stop
T2
T3
Device
Resume
“K” State
Host
Resume
T4
TMPA901CM
2010-07-29
SE0