TMPA901CMXBG Toshiba, TMPA901CMXBG Datasheet - Page 443

• Manufacturer Part Number: TMPA901CMXBG
• Description: Microcontrollers (MCU) 32-bit RISC MCU 16kb ARM926EJ 16kb 200Mhz
• Manufacturer: Toshiba

Specifications of TMPA901CMXBG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): -
• Rom Type: ROMless
• Ram (kbytes): 32
• Number Of Pins: 177
• Package: BGA
• Vcc: 3V
• Tft Lcd Controller: Y
• Touchscreen Controller: Y
• Usb Host Fs With Phy: Y
• Usb Device Hs With Phy: Y
• Sd Host Controller: -
• Cmos Image Sensor Interface: -
• I2s: 1
• Ssp (ch) Spi: 1
• I2mc/sio (ch): 1
• Uart/sio (ch): 2
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 8
• 10-bit Ad Converter: 4
• 12-bit Da Converter: -
• 16-bit Timer / Counter: 6
• Real Time Clock: Y
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Low-power Modes: Y
• Lead Free Status / Rohs Status: Details

[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
Bit
[Description]
int_nak
int_ep
int_ep0
int_sof
int_rx_zero
int_status
int_status_nak
int_setup
a. <int_mw_rerror>
b. <int_dmac_reg_rd>
c.
d. <int_mr_ahberr>
Will be set to 1 when the access to the endpoint has started Master Write transfer during
the setting of common bus access (bus_sel bit of EPx_Status register is 0).
0y0: Not detected
0y1: Endpoint read error occurred in Master Write
Will be set to 1 when the register access executed by the setting of DMAC Read Request
register is completed and the value read to DMAC Read Value register is set.
0y0: Not detected
0y1: Register read completed
<int_udc2_reg_rd>
Will be set to 1 when the UDC2 access executed by the setting of UDC2 Read Request
register is completed and the value read to UDC2 Read Value register is set.
Also set to 1 when Write access to the internal register of UDC2 is completed.
0y0: Not detected
0y1: Register read/write completed
This status will be set to 1 when the AHB error has occurred during the operation of
Master Read transfer.
After this interrupt has occurred, the Master Read transfer block needs to be reset by the
mr_reset bit of DMAC Setting register.
0y0: Not detected
0y1: AHB error occurred
Symbol
Bit
RO
RO
RO
RO
RO
RO
RO
RO
Type
0y0
0y0
0y0
0y0
0y0
0y0
0y0
0y0
Reset
Value
TMPA901CM- 442
UDC2_INT_NAK register
UDC2 INT_EP register
UDC2 INT_EP0 register
UDC2 INT_SOF register
UDC2 INT_RXDATA0 register
UDC2 INT_STATUS register
UDC2 INT_STATUS_NAK register
UDC2 INT_STATUS register
Description
TMPA901CM
2010-07-29