TMPA901CMXBG Toshiba, TMPA901CMXBG Datasheet - Page 150

• Manufacturer Part Number: TMPA901CMXBG
• Description: Microcontrollers (MCU) 32-bit RISC MCU 16kb ARM926EJ 16kb 200Mhz
• Manufacturer: Toshiba

Specifications of TMPA901CMXBG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): -
• Rom Type: ROMless
• Ram (kbytes): 32
• Number Of Pins: 177
• Package: BGA
• Vcc: 3V
• Tft Lcd Controller: Y
• Touchscreen Controller: Y
• Usb Host Fs With Phy: Y
• Usb Device Hs With Phy: Y
• Sd Host Controller: -
• Cmos Image Sensor Interface: -
• I2s: 1
• Ssp (ch) Spi: 1
• I2mc/sio (ch): 1
• Uart/sio (ch): 2
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 8
• 10-bit Ad Converter: 4
• 12-bit Da Converter: -
• 16-bit Timer / Counter: 6
• Real Time Clock: Y
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Low-power Modes: Y
• Lead Free Status / Rohs Status: Details

9. GPIODMIS (Port D Interrupt Status Register (Masked))
10. GPIODIC (Port D Interrupt Clear Register)
[31:8]
[7:6]
[5:0]
[31:8]
[7:6]
[5:0]
[Description]
[Description]
Bit
a. <PD7MIS to PD6MIS>
a. <PD7IC to PD6IC>
Bit
Note: Refer to Table 3.9.5 for the configurations of each external interrupt register.
the interrupt enable register.
Masked interrupt status register: Monitors the interrupt status after being masked by
0y0: Not requested
0y1: Requested
Interrupt clear register: Clears edge-sensitive interrupts.
0y0: Invalid
0y1: Request cleared
PD7MIS to PD6MIS
PD7IC to PD6IC
Symbol
Symbol
Bit
Bit
WO
RO
Type
Type
TMPA901CM-149
Undefined
0y00
Undefined
Undefined
0y00
Undefined
Reset
Value
Reset
Value
Read as undefined. Written as zero.
Port D interrupt clear register (for each bit)
0y0: Invalid
0y1: Request cleared
Read as undefined. Written as zero.
Read as undefined.
Port D masked interrupt status register (for
each bit)
0y0: Not requested
0y1: Requested
Read as undefined.
Address
Address
Description
Description
(0xF080_3000) + (0x081C)
(0xF080_3000) + (0x0818)
TMPA901CM
2010-07-29