TMPA901CMXBG Toshiba, TMPA901CMXBG Datasheet - Page 29

• Manufacturer Part Number: TMPA901CMXBG
• Description: Microcontrollers (MCU) 32-bit RISC MCU 16kb ARM926EJ 16kb 200Mhz
• Manufacturer: Toshiba

Specifications of TMPA901CMXBG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): -
• Rom Type: ROMless
• Ram (kbytes): 32
• Number Of Pins: 177
• Package: BGA
• Vcc: 3V
• Tft Lcd Controller: Y
• Touchscreen Controller: Y
• Usb Host Fs With Phy: Y
• Usb Device Hs With Phy: Y
• Sd Host Controller: -
• Cmos Image Sensor Interface: -
• I2s: 1
• Ssp (ch) Spi: 1
• I2mc/sio (ch): 1
• Uart/sio (ch): 2
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 8
• 10-bit Ad Converter: 4
• 12-bit Da Converter: -
• 16-bit Timer / Counter: 6
• Real Time Clock: Y
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Low-power Modes: Y
• Lead Free Status / Rohs Status: Details

3.2.4
3.2.5
machine. When the monitoring starts, the TAP controller determines the test functionality to be
implemented. This includes both loading the JTAG instruction register (IR) and beginning a
serial data scan through a data register (DR), as shown in Table 3.2.1. As the data is scanned,
the state of the TMS pin signals each new data word and indicates the end of the data stream.
The data register is selected according to the contents of the instruction register.
The processor contains the following JTAG controller and registers:
JTAG basically operates to monitor the TMS input signal with the TAP controller state
MSB
Instruction register
Boundary scan register
Bypass register
Device identification register
Test Access Port (TAP) controller
used to select the test to be performed and/or the test data register to be accessed. As listed
in Table 3.2.1, this instruction codes select either the boundary scan register or the bypass
register.
JTAG Controller and Registers
Instruction Register
Figure 3.2.2 shows the format of the instruction register.
Instruction code
The JTAG instruction register includes four shift register-based cells. This register is
The instruction code is shifted out to the instruction register from the LSB.
TDI
(MSB to LSB)
0100 to 1110
３
0000
0001
0010
0011
1111
Table 3.2.1 JTAG Instruction Register Bit Configuration
Figure 3.2.3 Instruction Register Shift Direction
MSB
Figure 3.2.2 Instruction register
SAMPLE/PRELOAD
Instruction
Reserved
BYPASS
EXTEST
TMPA901CM- 28
CLAMP
HIGHZ
２
Bypass Register
LSB
Selected data register
Boundary scan register
Boundary scan register
１
Bypass register
Bypass register
Bypass register
Reserved
TDO
LSB
TMPA901CM
2010-07-29
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