EP2AGX190FF35C6N Altera, EP2AGX190FF35C6N Datasheet - Page 85
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EP2AGX190FF35C6N
Manufacturer Part Number
EP2AGX190FF35C6N
Description
IC ARRIA II GX 190K 1152FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX190FF35C6N.pdf
(306 pages)
Specifications of EP2AGX190FF35C6N
Number Of Logic Elements/cells
181165
Number Of Labs/clbs
7612
Total Ram Bits
9939
Number Of I /o
612
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
190300
# I/os (max)
612
Frequency (max)
400MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
190300
Ram Bits
10380902.4
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Chapter 4: DSP Blocks in Arria II Devices
DSP Block Resource Descriptions
December 2010 Altera Corporation
Second Adder and Output Registers
1
You can use the rounding and saturation logic units together or independently.
The second adder register and output register banks are two banks of 44-bit registers
that you can combine to form larger 72-bit banks to support 36 × 36 output results.
The outputs of the different stages in the Arria II devices are routed to the output
registers through an output selection unit. Depending on the operational mode of the
DSP block, the output selection unit selects whether the outputs of the DSP blocks
come from the outputs of the multiplier block, first-stage adder, pipeline registers,
second-stage adder, or the rounding and saturation logic unit. Based on the DSP block
operational mode you specify, the output selection unit is automatically set by the
software, and has the option to either drive or bypass the output registers. The
exception is when the block is used in shift mode, where you dynamically control the
output-select multiplexer directly.
When the DSP block is configured in chained cascaded output mode, both of the
second-stage adders are used. The first adder is for performing a four-multiplier
adder and the second is for the chainout adder. The outputs of the four-multiplier
adder are routed to the second-stage adder registers before enters the chainout adder.
The output of the chainout adder goes to the regular output register bank. Depending
on the configuration, you can route the chainout results to the input of the next half
block’s chainout adder input or to the general fabric (functioning as regular output
registers).
You can only connect the chainin port to the chainout port of the previous DSP block
and must not be connected to general routings.
The second-stage and output registers are triggered by the positive edge of the clock
signal and are cleared on power up. The clock[3..0], ena[3..0], and aclr[3..0]
DSP block signals control the output registers in the DSP block.
Arria II Device Handbook Volume 1: Device Interfaces and Integration
4–13
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