EP2AGX190FF35C6N Altera, EP2AGX190FF35C6N Datasheet - Page 481

• Manufacturer Part Number: EP2AGX190FF35C6N
• Description: IC ARRIA II GX 190K 1152FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX190FF35C6N

• Number Of Logic Elements/cells: 181165
• Number Of Labs/clbs: 7612
• Total Ram Bits: 9939
• Number Of I /o: 612
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 190300
• # I/os (max): 612
• Frequency (max): 400MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 190300
• Ram Bits: 10380902.4
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 1: Transceiver Architecture in Arria II Devices
Transceiver Port List
Table 1–24. ALTGX Megafunction Word Aligner Ports for Arria II Devices (Part 1 of 2)
December 2010 Altera Corporation
rx_ala2size
rx_bitslip
rx_enapatternalign
rx_invpolarity
rx_revbitorderwa
rx_bitslipboundary
selectout
rx_patterndetect
Port Name
Table 1–24
megafunction.
Input/Output
Output
Output
Input
Input
Input
Input
Input
lists the word aligner port names and descriptions for the ALTGX
Available only in SONET OC-12 and OC-48 modes to select between one of the
following two word alignment options:
Logic Level
Asynchronous bit-slip control when the word aligner is configured in bit-slip
mode. At every rising edge of this signal, the word aligner slips one bit into the
received data stream, effectively shifting the word boundary by one bit.
The minimum pulse-width is two recovered clock cycles.
Asynchronous manual word alignment enable control. This signal is
edge-sensitive with 8-bit width data and level sensitive with 10-bit width data.
The minimum pulse-width is two recovered clock cycles.
Asynchronous receiver polarity inversion control. When asserted high, the
polarity of every bit of the 8-bit or 10-bit input data word to the word aligner is
inverted.
Asynchronous receiver bit reversal control. Available only in Basic mode with
the word aligner configured in bit-slip mode.
When asserted high in Basic mode, the 8-bit or 10-bit data D[7:0] or D[9:0]
at the output of the word aligner is rewired to D[0:7] or D[0:9], respectively.
Asynchronous signal indicating the number of bits slipped in the word aligner
when the word aligner is configured in manual mode.
Word alignment pattern detect indicator. A high level indicates that the word
alignment pattern is found on the current word boundary. The width of this
signal depends on the channel width shown below:
Channel Width
16/20
0
1
8/10
Word Alignment Pattern
32'bit A1A1A2A2
rx_patterndetect width
16-bit A1A2
1
2
Description
Arria II Device Handbook Volume 2: Transceivers
1–95