EP2AGX190FF35C6N Altera, EP2AGX190FF35C6N Datasheet - Page 507

• Manufacturer Part Number: EP2AGX190FF35C6N
• Description: IC ARRIA II GX 190K 1152FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX190FF35C6N

• Number Of Logic Elements/cells: 181165
• Number Of Labs/clbs: 7612
• Total Ram Bits: 9939
• Number Of I /o: 612
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 190300
• # I/os (max): 612
• Frequency (max): 400MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 190300
• Ram Bits: 10380902.4
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 2: Transceiver Clocking in Arria II Devices
Transceiver Channel Datapath Clocking
Figure 2–11. One PCIe ×8 Link in Two Transceiver Block Devices and Two PCIe ×8 Links in Four Transceiver Block
Arria II GZ Devices
Figure 2–12. Two PCIe ×8 Links in Six Transceiver Block Arria II GZ Devices
Note to
(1) Arria II GZ devices with six transceiver blocks allow a maximum of two PCIe ×8 links occupying four transceiver blocks. You can configure the
December 2010 Altera Corporation
other two transceiver blocks to implement other functional modes.
PCIe Lane 3
PCIe Lane 2
PCIe Lane 1
PCIe Lane 0
PCIe Lane 7
PCIe Lane 6
PCIe Lane 5
PCIe Lane 4
Figure
PCIe Lane 7
PCIe Lane 6
PCIe Lane 5
PCIe Lane 4
PCIe Lane 3
PCIe Lane 2
PCIe Lane 1
PCIe Lane 0
2–12:
Figure 2–11
Figure 2–12
EP2AGZ225F40, EP2AGZ300F40, EP2AGZ350F40
Transceiver Block
Transceiver Block
Transceiver Block
GXBL1 (Slave)
GXBL0(Master)
Transceiver Block GXBL0
Two PCIe x8 Link in Four Transceiver Block Devices
EP2AGZ225F35, EP2AGZ300H29, EP2AGZ300F35,
EP2AGZ350H29, EP2AGZ350F35
Transceiver Block GXBL1
Channel3
Channel2
Channel1
Channel0
Channel3
Channel2
Channel1
Channel0
Channel3
Channel2
Channel1
Channel0
GXBL2
Channel3
Channel2
Channel1
Channel0
Channel3
Channel2
Channel1
Channel0
(Master)
(Slave)
shows two PCIe ×8 links in four transceiver block Arria II GZ devices.
shows two PCIe ×8 links in six transceiver block Arria II GZ devices.
Second PCIe
Second PCIe
x8 Link
x8 Link
One PCIe x8 Link in Two Transceiver Block Devices
First PCIe
x8 Link
First PCIe
x8 Link
Transceiver Block GXBR1
Transceiver Block GXBR0
(Note 1)
Channel3
Channel2
Channel1
Channel0
Channel3
Channel2
Channel1
Channel0
(Master)
(Slave)
Transceiver Block
Transceiver Block
Transceiver Block
GXBR0 (Master)
Arria II Device Handbook Volume 2: Transceivers
GXBR1 (Slave)
Channel3
Channel2
Channel1
Channel0
Channel3
Channel2
Channel1
Channel0
Channel3
Channel2
Channel1
Channel0
GXBR2
PCIe Lane 7
PCIe Lane 6
PCIe Lane 5
PCIe Lane 4
PCIe Lane 3
PCIe Lane 2
PCIe Lane 1
PCIe Lane 0
PCIe Lane 3
PCIe Lane 2
PCIe Lane 1
PCIe Lane 0
PCIe Lane 7
PCIe Lane 6
PCIe Lane 5
PCIe Lane 4
2–17