EP2AGX190FF35C6N Altera, EP2AGX190FF35C6N Datasheet - Page 59
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EP2AGX190FF35C6N
Manufacturer Part Number
EP2AGX190FF35C6N
Description
IC ARRIA II GX 190K 1152FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX190FF35C6N.pdf
(306 pages)
Specifications of EP2AGX190FF35C6N
Number Of Logic Elements/cells
181165
Number Of Labs/clbs
7612
Total Ram Bits
9939
Number Of I /o
612
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
190300
# I/os (max)
612
Frequency (max)
400MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
190300
Ram Bits
10380902.4
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Chapter 3: Memory Blocks in Arria II Devices
Memory Modes
Table 3–5. M9K Block Mixed-Width Configurations (Simple Dual-Port Mode)
Table 3–6. M144K Block Mixed-Width Configurations (Simple Dual-Port Mode)
December 2010 Altera Corporation
8K × 1
4K × 2
2K × 4
1K × 8
512 × 16
256 × 32
1K × 9
512 × 18
256 × 36
16K × 8
8K × 16
4K × 32
2K × 64
16K × 9
8K × 18
4K × 36
2K × 72
Read Port
Read Port
Simple dual-port mode supports different read and write data widths (mixed width
support).
dual-port mode. MLABs do not have native support for mixed width operations. The
Quartus II software can implement mixed width memories in MLABs with more than
one MLAB.
Table 3–6
mode.
In simple dual-port mode, M9K and M144K blocks support separate write-enable and
read-enable signals. Read-during-write operations to the same address can either
output a “don’t care” or “old data” value.
MLABs only support a write-enable signal. Read-during-write behavior for the
MLABs can be either a “don’t care” or “old data” value. The available choices depend
on the configuration of the MLAB.
8K × 1
v
v
v
v
v
v
16K × 8
—
—
—
v
v
v
v
—
—
—
—
4K × 2
Table 3–5
lists the mixed-width configurations for M144K blocks in simple dual-port
v
v
v
v
v
v
—
—
—
8K × 16
v
v
v
v
—
—
—
—
2K × 4
lists the mixed width configurations for the M9K blocks in simple
v
v
v
v
v
v
—
—
—
4K × 32
v
v
v
v
—
—
—
—
1K × 8
v
v
v
v
v
v
—
—
—
2K × 64
512 × 16
Arria II Device Handbook Volume 1: Device Interfaces and Integration
v
v
v
v
—
—
—
—
Write Port
v
v
v
v
v
v
—
—
—
Write Port
16K × 9
256 × 32
v
v
v
v
—
—
—
—
v
v
v
v
v
v
—
—
—
8K × 18
1K × 9
v
v
v
v
—
—
—
—
—
—
—
—
—
—
v
v
v
512 × 18
4K × 36
—
—
—
—
—
—
v
v
v
—
—
—
—
v
v
v
v
256 × 36
2K × 72
—
—
—
—
—
—
v
v
v
—
—
—
—
v
v
v
v
3–13
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