EP2AGX190FF35C6N Altera, EP2AGX190FF35C6N Datasheet - Page 430

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EP2AGX190FF35C6N

Manufacturer Part Number
EP2AGX190FF35C6N
Description
IC ARRIA II GX 190K 1152FBGA
Manufacturer
Altera
Series
Arria II GXr

Specifications of EP2AGX190FF35C6N

Number Of Logic Elements/cells
181165
Number Of Labs/clbs
7612
Total Ram Bits
9939
Number Of I /o
612
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
190300
# I/os (max)
612
Frequency (max)
400MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
190300
Ram Bits
10380902.4
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant

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1–44
Figure 1–44. MSByte and LSByte of the Two-Byte Transmitter Data Straddled Across Two Word Boundaries
Arria II Device Handbook Volume 2: Transceivers
tx_datain[15:8]
tx_datain[7:0]
D2
D1
D4
D3
Byte Ordering
Depending on when the receiver PCS logic comes out of reset, byte ordering at the
output of the byte deserializer may not match the original byte ordering of the
transmitted data. The byte misalignment resulting from byte deserialization is
unpredictable because it depends on which byte is being received by the byte
deserializer when it comes out of reset.
Figure 1–71
transmitter data appears straddled across two word boundaries after getting byte
deserialized at the receiver.
The byte ordering block looks for the user-programmed byte ordering pattern in the
byte-deserialized data. You must select a byte ordering pattern that you know appears
at the LSByte(s) position of the parallel transmitter data. If the byte ordering block
finds the programmed byte ordering pattern in the MSbyte(s) position of the
byte-deserialized data, it inserts the appropriate number of user-programmed PAD
bytes to push the byte ordering pattern to the LSByte(s) position, thereby restoring
proper byte ordering.
The byte ordering block is available in the following functional modes:
Transmitter
D6
D5
SONET/SDH OC-48—The Quartus II software automatically configures the byte
ordering pattern and byte ordering PAD pattern in this mode.
SONET/SDH OC-96—For Arria II GZ devices only.
Basic mode with 16-bit FPGA fabric-to-transceiver interface, no 8B/10B decoder
(8-bit PMA-PCS interface) and word aligner in manual alignment mode—You can
program a custom 8-bit byte ordering pattern and 8-bit byte ordering PAD pattern
in the ALTGX MegaWizard Plug-In Manager.
Basic mode with 16-bit FPGA fabric-to-transceiver interface, 8B/10B decoder, and
word aligner in automatic synchronization state machine mode—You can
program a custom 9-bit byte ordering pattern and 9-bit byte ordering PAD pattern
in the ALTGX MegaWizard Plug-In Manager. If a /Kx.y/ control code group is
selected as the byte ordering pattern, the MSB of the 9-bit byte ordering pattern
must be 1'b1. If a /Dx.y/ data code group is selected as the byte ordering pattern,
the MSB of the 9-bit byte ordering pattern must be 1'b0. The least significant 8 bits
must be the 8B/10B decoded version of the code group used for byte ordering.
Serializer
shows a scenario in which the MSByte and LSByte of the two-byte
Byte
xx D1 D2 D3 D4 D5 D6 xx
Deserializer
Byte
Chapter 1: Transceiver Architecture in Arria II Devices
Receiver
D1
XX
December 2010 Altera Corporation
D3
D2
D5
D4
Receiver Channel Datapath
XX
D6
rx_dataout[15:8]
rx_dataout[7:0]

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