EP2AGX190FF35C6N Altera, EP2AGX190FF35C6N Datasheet - Page 159

• Manufacturer Part Number: EP2AGX190FF35C6N
• Description: IC ARRIA II GX 190K 1152FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX190FF35C6N

• Number Of Logic Elements/cells: 181165
• Number Of Labs/clbs: 7612
• Total Ram Bits: 9939
• Number Of I /o: 612
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 190300
• # I/os (max): 612
• Frequency (max): 400MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 190300
• Ram Bits: 10380902.4
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

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AIIGX51006-4.0
Arria II Device Handbook Volume 1: Device Interfaces and Integration
December 2010
December 2010
AIIGX51006-4.0
This chapter describes how Arria
to work in compliance with current and emerging I/O standards and requirements.
With these device features, you can reduce board design interface costs and increase
development flexibility.
Package and die enhancements with dynamic termination and output control provide
best-in-class signal integrity. Numerous I/O features assist high-speed data transfer
into and out of the device, including:
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This chapter includes the following sections:
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Single-ended, non-voltage-referenced, and voltage-referenced I/O standards
Low-voltage differential signaling (LVDS), reduced swing differential signal
(RSDS), mini-LVDS, high-speed transceiver logic (HSTL), and SSTL
Bus LVDS (BLVDS) for Arria II GX devices
Programmable output current strength
Programmable slew rate
Programmable bus-hold
Programmable pull-up resistor
Open-drain output
On-chip series termination (R
On-chip differential termination (R
On-chip parallel termination (R
Dynamic OCT for Arria II GZ devices
Programmable pre-emphasis
Programmable voltage output differential (V
“I/O Standards Support” on page 6–2
“I/O Banks” on page 6–5
“I/O Structure” on page 6–10
“OCT Support” on page 6–19
“Arria II OCT Calibration” on page 6–26
“Termination Schemes for I/O Standards” on page 6–28
“I/O Bank Restrictions” on page 6–36
6. I/O Features in Arria II Devices
S
®
OCT)
II devices provide I/O capabilities that allow you
T
OCT) for Arria II GZ devices
D
OCT)
OD
)
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