EP2AGX190FF35C6N Altera, EP2AGX190FF35C6N Datasheet - Page 324
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EP2AGX190FF35C6N
Manufacturer Part Number
EP2AGX190FF35C6N
Description
IC ARRIA II GX 190K 1152FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX190FF35C6N.pdf
(306 pages)
Specifications of EP2AGX190FF35C6N
Number Of Logic Elements/cells
181165
Number Of Labs/clbs
7612
Total Ram Bits
9939
Number Of I /o
612
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
190300
# I/os (max)
612
Frequency (max)
400MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
190300
Ram Bits
10380902.4
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- EP2AGX45CU17C6N PDF datasheet
- EP2AGX45CU17C6N PDF datasheet #2
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- EP2AGX45CU17C6N PDF datasheet #4
- EP2AGX45CU17C6N PDF datasheet #5
- EP2AGX190FF35C6N PDF datasheet #6
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9–44
Table 9–17. Optional Configuration Pins
Arria II Device Handbook Volume 1: Device Interfaces and Integration
CLKUSR
INIT_DONE
DEV_OE
DEV_CLRn
Pin Name
N/A if option is on.
N/A if option is on.
N/A if option is on.
N/A if option is on.
I/O if option is off.
I/O if option is off.
I/O if option is off.
I/O if option is off.
Table 9–17
are not enabled in the Quartus II software, they are available as general-purpose user
I/O pins. Therefore, during configuration, these pins function as user I/O pins and
are tri-stated with weak pull-up resistors.
User Mode
lists the optional configuration pins. If these optional configuration pins
Chapter 9: Configuration, Design Security, and Remote System Upgrades in Arria II Devices
open-drain
Pin Type
Output
Input
Input
Input
Optional user-supplied clock input synchronizes the
initialization of one or more devices. Enable this pin by turning
on the Enable user-supplied start-up clock (CLKUSR) option
in the Quartus II software.
Use as a status pin to indicate when the device has initialized
and is in user mode. When nCONFIG is low and during the
beginning of configuration, the INIT_DONE pin is tri-stated
and pulled high due to an external 10-kΩ pull-up resistor.
After the option bit to enable INIT_DONE is programmed into
the device (during the first frame of configuration data), the
INIT_DONE pin goes low. When initialization is complete, the
INIT_DONE pin is released and pulled high and the device
enters user mode. Thus, the monitoring circuitry must be able
to detect a low-to-high transition. Enable this pin by turning
on the Enable INIT_DONE output option in the Quartus II
software.
Optional pin that allows you to override all tri-states on the
device. When this pin is driven low, all I/O pins are tri-stated.
When this pin is driven high, all I/O pins behave as
programmed. Enable this pin by turning on the Enable
device-wide output enable (DEV_OE) option in the Quartus II
software.
Optional pin that allows you to override all clears on all device
registers. When this pin is driven low, all registers are cleared.
When this pin is driven high, all registers behave as
programmed. Enable this pin by turning on the Enable
device-wide reset (DEV_CLRn) option in the Quartus II
software.
Description
December 2010 Altera Corporation
Device Configuration Pins
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