EP2AGX190FF35C6N Altera, EP2AGX190FF35C6N Datasheet - Page 503

• Manufacturer Part Number: EP2AGX190FF35C6N
• Description: IC ARRIA II GX 190K 1152FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX190FF35C6N

• Number Of Logic Elements/cells: 181165
• Number Of Labs/clbs: 7612
• Total Ram Bits: 9939
• Number Of I /o: 612
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 190300
• # I/os (max): 612
• Frequency (max): 400MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 190300
• Ram Bits: 10380902.4
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 2: Transceiver Clocking in Arria II Devices
Transceiver Channel Datapath Clocking
December 2010 Altera Corporation
×8 Bonded Channel Configuration
The PCIe ×8 and Basic ×8 functional modes support ×8 bonded channel configuration
in Arria II GX and GZ devices with two transceiver blocks. The eight bonded channels
are located in two transceiver blocks, referred to as the master transceiver block and
slave transceiver block, with four channels each. The CMU0 clock divider in the CMU0
block of the master transceiver block provides the serial PMA clock and parallel PCS
clock to all eight bonded channels. The serializer in the transmitter channel PMA of
the eight bonded channels uses the same low-speed parallel clock and high-speed
serial clock from the CMU0 of the master transceiver block for their parallel-in,
serial-out operation. The low-speed parallel clock from the CMU0 of the master
transceiver block clocks the 8B/10B encoder and read port of the byte serializer (if
enabled) in the transmitter channel PCS of all eight channels.
For an 8-bit FPGA fabric-transceiver channel interface that does not use the byte
serializer, the low-speed parallel clock from the CMU0 clock divider block in the master
transceiver block clocks the read port of the transmitter phase compensation FIFO in
all eight bonded channels. This low-speed parallel clock is also driven directly on the
coreclkout port as the FPGA fabric-transceiver interface clock. You can use the
coreclkout signal to clock the transmitter data and control logic in the FPGA fabric
for all eight bonded channels.
For a 16-bit FPGA fabric-transceiver channel interface that uses the byte serializer, the
low-speed parallel clock from the CMU0 clock divider block in the master transceiver
block is divided by two. This divide-by-two version of the low-speed parallel clock
provides a clock to the write port of the byte serializer and the read port of the
transmitter phase compensation FIFO in all eight bonded channels. It is also driven on
the coreclkout port as the FPGA fabric-transceiver interface clock. You can use the
coreclkout signal to clock the transmitter data and control logic in the FPGA fabric
for all eight bonded channels.
In the ×8 bonded channel configuration, the transmitter phase compensation FIFOs in
all eight bonded channels share common read and write pointers and enable signals
generated in the CMU0 block of the master transceiver block, ensuring equal
transmitter phase compensation FIFO latency across all eight bonded channels,
resulting in low transmitter channel-to-channel skew.
Arria II Device Handbook Volume 2: Transceivers
2–13