EP2AGX190FF35C6N Altera, EP2AGX190FF35C6N Datasheet - Page 395

• Manufacturer Part Number: EP2AGX190FF35C6N
• Description: IC ARRIA II GX 190K 1152FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX190FF35C6N

• Number Of Logic Elements/cells: 181165
• Number Of Labs/clbs: 7612
• Total Ram Bits: 9939
• Number Of I /o: 612
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 190300
• # I/os (max): 612
• Frequency (max): 400MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 190300
• Ram Bits: 10380902.4
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 1: Transceiver Architecture in Arria II Devices
Clock Multiplier Units (CMU)
Figure 1–7. Diagram of the CMU PLL
Notes to
(1) The ITB clock lines shown are the maximum value. The actual number of ITB lines in your device depends on the number of transceiver blocks
(2) Although each CMU PLL has its own pll_powerdown port, the ALTGX MegaWizard Plug-In Manager instantiation provides only one port per
(3) There is one pll_locked signal per CMU PLL.
December 2010 Altera Corporation
PLL Cascade Clock
ITB Clock Lines (1)
pll_powerdown (2)
Global Clock Line
Dedicated refclk0
Dedicated refclk1
on one side of the device.
transceiver block. This port power downs one or both CMU PLLs (if used).
Figure
CMU PLL
1–7:
f
f
1
CMU PLL
6
Figure 1–7
For more information about input reference clocks, refer to the “CMU PLL and
Receiver CDR Input Reference Clocks” section of the
Devices
The phase frequency detector (PFD) in the CMU PLL tracks the voltage-controlled
oscillator (VCO) output with the input reference clock. This VCO runs at half the
serial data rate. The CMU PLL generates the high-speed clock from the input
reference clock through the two divider blocks (/M and /L) in the feedback path.
Table 1–3
Quartus
rate.
Table 1–3. Multiplier Block Heading to Clock Divider for Arria II Devices
You can set the PLL bandwidth in the ALTGX megafunction.
The high-speed clock output from the CMU PLL is forwarded to the CMU0 clock
divider block in bonded functional modes and the transmitter channel local clock
divider block in non-bonded functional modes. The output of either clock divider
block provides clocks for the PCS and PMA blocks.
For more information about using two CMU PLLs to configure multiple transmitter
channels, refer to the
chapter.
Input Reference
chapter.
®
CMU PLL
lists the available /M and /L settings, which are set automatically in the
Clock
II software, based on the input reference clock frequency and serial data
shows the block diagram of the CMU PLL.
Multiplier Block
/1, /2, /4, /8
/M
/L
Configuring Multiple Protocols and Data Rates in Arria II Devices
Detect
PFD
Lock
Charge Pump
+ Loop Filter
/M
Arria II Device Handbook Volume 2: Transceivers
Transceiver Clocking in Arria II
1, 4, 5, 8, 10, 16, 20, 25
VCO
Available Values
1, 2, 4
/L
pll_locked (3)
CMU PLL
High-Speed Clock
1–9