EP2AGX190FF35C6N Altera, EP2AGX190FF35C6N Datasheet - Page 535
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EP2AGX190FF35C6N
Manufacturer Part Number
EP2AGX190FF35C6N
Description
IC ARRIA II GX 190K 1152FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX190FF35C6N.pdf
(306 pages)
Specifications of EP2AGX190FF35C6N
Number Of Logic Elements/cells
181165
Number Of Labs/clbs
7612
Total Ram Bits
9939
Number Of I /o
612
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
190300
# I/os (max)
612
Frequency (max)
400MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
190300
Ram Bits
10380902.4
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- EP2AGX45CU17C6N PDF datasheet
- EP2AGX45CU17C6N PDF datasheet #2
- EP2AGX45CU17C6N PDF datasheet #3
- EP2AGX45CU17C6N PDF datasheet #4
- EP2AGX45CU17C6N PDF datasheet #5
- EP2AGX190FF35C6N PDF datasheet #6
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- Download datasheet (22Mb)
Chapter 2: Transceiver Clocking in Arria II Devices
FPGA Fabric-Transceiver Interface Clocking
Figure 2–25. FPGA Fabric-Receiver Interface Clocking for Example 7
December 2010 Altera Corporation
Channel PMA
Channel PMA
Channel PMA
Channel PMA
Channel PMA
Channel PMA
Channel PMA
Channel PMA
Transceiver
Transceiver
Transceiver
Transceiver
Divider Block
Divider Block
Divider Block
Divider Block
Local Clock
Local Clock
Local Clock
Local Clock
Receiver
Receiver
Receiver
Receiver
Channel 3
Channel 2
Channel 1
Channel 0
Receiver Channel PCS
Low-Speed Parallel Clock
Receiver Channel PCS
Low-Speed Parallel Clock
CMU1 Block
CMU0 Block
Receiver Channel PCS
Low-Speed Parallel Clock
Receiver Channel PCS
Low-Speed Parallel Clock
Figure 2–25
shows FPGA fabric-receiver interface clocking for Example 7.
Parallel Data
Parallel Data
Parallel Data
Parallel Data
/2
/2
/2
/2
CMU1
CMU0
PLL
PLL
Compensation
Compensation
Compensation
Compensation
rdclk
rdclk
rdclk
rdclk
RX Phase
RX Phase
RX Phase
RX Phase
FIFO
FIFO
Reference Clock
Reference Clock
FIFO
FIFO
wrclk
tx_clkout[2]
tx_clkout[0]
wrclk
wrclk
wrclk
Arria II Device Handbook Volume 2: Transceivers
FPGA Fabric
rx_coreclk[3]
rx_coreclk[2]
rx_coreclk[1]
rx_coreclk[0]
and Status
and Status
and Status
and Status
Channel 3
Channel 2
Channel 1
Channel 0
RX Data
RX Data
RX Data
RX Data
Logic
Logic
Logic
Logic
2–45
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