EP2AGX190FF35C6N Altera, EP2AGX190FF35C6N Datasheet - Page 418

• Manufacturer Part Number: EP2AGX190FF35C6N
• Description: IC ARRIA II GX 190K 1152FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX190FF35C6N

• Number Of Logic Elements/cells: 181165
• Number Of Labs/clbs: 7612
• Total Ram Bits: 9939
• Number Of I /o: 612
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 190300
• # I/os (max): 612
• Frequency (max): 400MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 190300
• Ram Bits: 10380902.4
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

1–32
Table 1–10. Word Aligner Modes for Arria II Devices
Arria II Device Handbook Volume 2: Transceivers
Manual Alignment
Bit-Slip
Automatic Synchronization
State Machine
Word Aligner Mode
■
Figure 1–33. 10-Bit Receiver Bit Reversal in Basic Mode with Word Aligner in Bit-Slip Mode
Table 1–10
functional mode, and allowed alignment pattern length for Arria II devices.
Receiver bit reversal—This feature is only available in Basic mode. By default, the
Arria II GX and GZ receiver assumes LSB-to-MSB transmission. If the transmission
order is MSB-to-LSB, the receiver forwards the bit-flipped version of the parallel
data to the FPGA fabric on the rx_dataout port. The receiver bit reversal feature is
available to correct this situation by flipping the parallel data so that the
rx_dataout port contains the correct bit-ordered data.
This feature is available through the rx_revbitordwa port in Basic mode only with
the word aligner configured in bit-slip mode. When you drive the rx_revbitordwa
signal high in this configuration, the 8-bit or 10-bit data D[7:0] or D[9:0] at the
output of the word aligner gets rewired to D[0:7] or D[0:9], respectively.
Figure 1–33
datapath configurations.
Supported (bits)
Data Width
lists the three modes of the word aligner and their supported data width,
10
16
20
10
16
20
10
8
8
shows the receiver bit reversal feature in Basic mode with 10-bit wide
Output of Word Aligner Before
RX Bit Reversal
Basic, GIGE, PCIe, Serial RapidIO,
Basic and Deterministic Latency
Basic and Deterministic Latency
Basic and Deterministic Latency
Basic and Deterministic Latency
Basic and Deterministic Latency
Functional Mode Supported
Basic, OC-12, and OC-48
D[9]
D[8]
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
Basic and SDI
and XAUI
rx_revbitordwa = HIGH
Basic
Chapter 1: Transceiver Architecture in Arria II Devices
Output of Word Aligner
After RX Bit Reversal
Allowed Word Alignment Pattern
10 bits for all functional modes
D[0]
D[1]
D[2]
D[3]
D[4]
D[5]
D[6]
D[7]
D[8]
D[9]
7 bits or 10 bits for Basic
December 2010 Altera Corporation
7 or 10 bits for Basic
8, 16, or 32 bits
7, 10, or 20 bits
8, 16, or 32 bits
7, 10, or 20 bits
7 or 10 bits
N/A for SDI
Receiver Channel Datapath
Length
16 bits
16 bits