EP2AGX190FF35C6N Altera, EP2AGX190FF35C6N Datasheet - Page 115

• Manufacturer Part Number: EP2AGX190FF35C6N
• Description: IC ARRIA II GX 190K 1152FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX190FF35C6N

• Number Of Logic Elements/cells: 181165
• Number Of Labs/clbs: 7612
• Total Ram Bits: 9939
• Number Of I /o: 612
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 190300
• # I/os (max): 612
• Frequency (max): 400MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 190300
• Ram Bits: 10380902.4
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 5: Clock Networks and PLLs in Arria II Devices
Clock Networks in Arria II Devices
Table 5–6. PLLs and PLL Clock Pin Drivers for Arria II GX Devices
Table 5–7. PLLs and PLL Clock Pin Drivers for Arria II GZ Devices
December 2010 Altera Corporation
CLK[4..7]
CLK[8..11]
CLK[12..15]
Note to
(1) PLL_5 and PLL_6 are connected directly to CLK[8..11]. PLL_1, PLL_2, PLL_3 and PLL_4 are driven by the clock input pins through a 4:1
CLK[0..3]
CLK[4..7]
CLK[8..11]
CLK[12..15]
Notes to
(1) For single-ended clock inputs, only the CLK<#>p pin has a dedicated connection to the PLL. If you use the CLK<#>n pin, a GCLK is used.
(2) For the availability of the clock input pins in each device density, refer to the “Arria II Device Pin-Out Files” section of the
Dedicated Clock Input Pin CLK
multiplexer.
Devices.
Dedicated Clock Input Pin CLK (p/n Pins)
Table
Table
Clock Input Connections to PLLs
Clock Output Connections
5–6:
5–7:
(p/n Pins)
Table 5–6
PLLs in Arria II GX devices can drive up to 24 RCLK networks and eight GCLK
networks, while PLLs in Arria II GZ devices can drive up to 20 RCLK networks and
four GCLK networks. The Quartus
outputs to RCLK or GCLK networks.
and
Table 5–7
—
—
—
L2
v
list dedicated clock input pin connectivity to Arria II PLLs.
—
—
—
L3
v
—
—
v
1
®
B1
v
—
—
—
Arria II Device Handbook Volume 1: Device Interfaces and Integration
II software automatically assigns PLL clock
(Note
(Note 1)
—
2
v
v
1),
B2
—
—
—
v
PLL Number
(2)
PLL Number
—
3
v
v
R2
—
—
—
v
—
—
v
4
R3
—
—
—
v
Pin-Out Files for Altera
—
—
v
5
v
T1
—
—
—
—
—
v
6
T2
—
—
—
v
5–11