EP2AGX190FF35C6N Altera, EP2AGX190FF35C6N Datasheet - Page 443
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EP2AGX190FF35C6N
Manufacturer Part Number
EP2AGX190FF35C6N
Description
IC ARRIA II GX 190K 1152FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX190FF35C6N.pdf
(306 pages)
Specifications of EP2AGX190FF35C6N
Number Of Logic Elements/cells
181165
Number Of Labs/clbs
7612
Total Ram Bits
9939
Number Of I /o
612
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
190300
# I/os (max)
612
Frequency (max)
400MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
190300
Ram Bits
10380902.4
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Chapter 1: Transceiver Architecture in Arria II Devices
Functional Modes
Figure 1–55. Deterministic Latency Functional Mode
Notes to
(1) The transmitter is in bit-slip mode.
(2) This block is optional in this mode.
(3) The RX phase compensation FIFO is automatically set in register mode. However, you have the option to set the TX phase compensation FIFO in
(4) Typically, the 8B/10B encoder and decoder are used when you use deterministic latency to implement CPRI or OBSAI protocols. However, you
(5) TX PCS latency (FPGA fabric-transceiver interface clock cycles) = 4.
(6) RX PCS latency (FPGA fabric-transceiver interface clock cycles) = 8 without byte DESER, 6 with byte DESER.
December 2010 Altera Corporation
Fabric
FPGA
register mode, which is not set by default.
have the option to disable this module.
Figure
GIGE
1–55:
Figure 1–55
IEEE 802.3 defines the 1000 Base-X PHY as an intermediate, or transition, layer that
interfaces various physical media with the media access control (MAC) in a GIGE
system. It shields the MAC layer from the specific nature of the underlying medium.
The 1000 Base-X PHY, which has a physical interface data rate of 1.25 Gbps, is divided
into three sublayers—the physical coding sublayer (PCS), physical media attachment
(PMA), and physical medium dependent (PMD). These sublayers interface with the
MAC through the gigabit medium independent interface (GMII).
tx_clkout[0]
Compensation
wrclk
shows the block diagram for deterministic latency.
TX Phase
FIFO (3)
rdclk
/2
wrclk
Byte Serializer
Receiver Channel PCS (6)
Transmitter Channel PCS (5)
(2)
/2
Low-Speed Parallel Clock from Clock Divider
rdclk
8B/10B Encoder
Low-Speed Parallel Clock from Clock Divider
(4)
Arria II Device Handbook Volume 2: Transceivers
Parallel Recovered Clock
Transmitter Channel
Receiver Channel
Recovered Clock
Local Clock
PMA (1)
Divider
Parallel
PMA
1–57
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