EP2AGX190FF35C6N Altera, EP2AGX190FF35C6N Datasheet - Page 313

• Manufacturer Part Number: EP2AGX190FF35C6N
• Description: IC ARRIA II GX 190K 1152FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX190FF35C6N

• Number Of Logic Elements/cells: 181165
• Number Of Labs/clbs: 7612
• Total Ram Bits: 9939
• Number Of I /o: 612
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 190300
• # I/os (max): 612
• Frequency (max): 400MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 190300
• Ram Bits: 10380902.4
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 9: Configuration, Design Security, and Remote System Upgrades in Arria II Devices
JTAG Configuration
JTAG Configuration
Table 9–13. JTAG Pins Signals (Part 1 of 2)
December 2010 Altera Corporation
TDI
TDO
Name
Pin
Test data
input
Test data
output
Pin Type
f
f
1
1
JTAG has developed a specification for boundary-scan testing. This boundary-scan
test (BST) architecture offers the capability to efficiently test components on PCBs
with tight lead spacing. The BST architecture can test pin connections without using
physical test probes and capture functional data while a device is operating normally.
You can also use JTAG circuitry to shift configuration data into the device. The
Quartus II software automatically generates .sofs that you can use for JTAG
configuration with a download cable in the Quartus II software programmer.
For more information about JTAG boundary-scan testing and commands available
using Arria II devices, refer to the following documents:
■
■
Arria II devices are designed such that JTAG instructions have precedence over any
device configuration modes. Therefore, JTAG configuration can take place without
waiting for other configuration modes to complete. For example, if you attempt JTAG
configuration of Arria II devices during PS configuration, PS configuration is
terminated and JTAG configuration begins.
You cannot use the Arria II decompression or design security features if you are
configuring your Arria II device using JTAG-based configuration.
A device operating in JTAG mode uses four required pins, TDI, TDO, TMS, and TCK, and
one optional pin, TRST. The TCK pin has an internal weak pull-down resistor, while the
TDI, TMS, and TRST pins have weak internal pull-up resistors (typically 25 kΩ ). All the
JTAG pins are powered by the V
devices and 2.5-V/3.0-V V
pins support only the LVTTL I/O standard.
All user I/O pins are tri-stated during JTAG configuration.
function of each JTAG pin.
For more information about how to connect a JTAG chain with multiple voltages
across the devices in the chain, refer to the
Devices
Serial input pin for instructions as well as test and programming data. Data is shifted in on the
rising edge of TCK. If the JTAG interface is not required on your board, you can disable the JTAG
circuitry by connecting this pin to logic high.
Serial data output pin for instructions as well as test and programming data. Data is shifted out on
the falling edge of TCK. The pin is tri-stated if data is not being shifted out of the device. If the
JTAG interface is not required on your board, you can disable the JTAG circuitry by leaving this pin
unconnected.
JTAG Boundary-Scan Testing in Arria II Devices
Programming Support for Jam STAPL Language
chapter.
CCPD
power supply for Arria II GZ devices. All the JTAG
CCIO
Arria II Device Handbook Volume 1: Device Interfaces and Integration
power supply of I/O bank 8C for Arria II GX
Description
JTAG Boundary-Scan Testing in Arria II
chapter
Table 9–13
lists the
9–33