EP2AGX190FF35C6N Altera, EP2AGX190FF35C6N Datasheet - Page 571
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EP2AGX190FF35C6N
Manufacturer Part Number
EP2AGX190FF35C6N
Description
IC ARRIA II GX 190K 1152FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX190FF35C6N.pdf
(306 pages)
Specifications of EP2AGX190FF35C6N
Number Of Logic Elements/cells
181165
Number Of Labs/clbs
7612
Total Ram Bits
9939
Number Of I /o
612
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
190300
# I/os (max)
612
Frequency (max)
400MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
190300
Ram Bits
10380902.4
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Chapter 3: Configuring Multiple Protocols and Data Rates in Arria II Devices
Combining Transceiver Instances in Multiple Transceiver Blocks
Combining Transceiver Instances in Multiple Transceiver Blocks
December 2010 Altera Corporation
f
If you use the PLL cascade clock to provide input reference clocks to the CMU PLLs or
RX CDRs, there are requirements for combining transceiver channels (as described in
the following sections).
The Arria II GX and GZ transceiver can cascade the output of the general purpose
PLLs to the CMU PLLs and receiver CDRs. The left side of the Arria II GX and GZ
device contains a PLL cascade clock network—a single line network that connects the
PLL cascade clock to the transceiver block. Similarly, for Arria II GZ devices, the right
side PLLs can only be cascaded with the transceivers on the right side of the device.
Each side of the Arria II GZ device contains a PLL cascade clock network. This clock
line is segmented to allow different PLL cascade clocks to drive the transceiver CMU
PLLs and RX CDRs.
The segmentation locations differ based on the device family. Therefore, there are
restrictions when you want to combine transceiver channels that use different PLL
cascade clocks as input reference clocks.
For more information about using the PLL cascade clock and segmentation, refer to
the “PLL Cascading” section in the
“Creating Transceiver Channel Instances” on page 3–2
instantiate multiple transceiver channels using a single ALTGX instance. The
following section describes the method to instantiate multiple transceiver channels
using multiple transceiver blocks.
When you create a transceiver instance that has more than four transceiver channels,
the Quartus II software attempts to combine the transceiver channels in multiple
transceiver blocks, as shown in
Example 4
Consider that you create two ALTGX instances with the configuration shown in
Table
Table 3–8. Two ALTGX Instances for Example 4 for Arria II Devices
In this case, assuming that all the required parameters specified in
Channels Sharing a CMU PLL” on page 3–3
Quartus II software fits inst0 and inst1 in two transceiver blocks.
Instance Name
3–8.
inst0
inst1
Transceiver
Number of
Channels
7
1
Example
Receiver and Transmitter
Receiver and Transmitter
Transceiver Clocking in Arria II Devices
Configuration
4.
are identical in inst0 and inst1, the
Arria II Device Handbook Volume 2: Transceivers
describes the method to
Effective Data
Rate (Gbps)
3.125
3.125
“Multiple
Clock (Gbps)
chapter.
Reference
156.25
156.25
Input
3–13
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