EP2AGX190FF35C6N Altera, EP2AGX190FF35C6N Datasheet - Page 407
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EP2AGX190FF35C6N
Manufacturer Part Number
EP2AGX190FF35C6N
Description
IC ARRIA II GX 190K 1152FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX190FF35C6N.pdf
(306 pages)
Specifications of EP2AGX190FF35C6N
Number Of Logic Elements/cells
181165
Number Of Labs/clbs
7612
Total Ram Bits
9939
Number Of I /o
612
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
190300
# I/os (max)
612
Frequency (max)
400MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
190300
Ram Bits
10380902.4
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Chapter 1: Transceiver Architecture in Arria II Devices
Receiver Channel Datapath
Receiver Channel Datapath
Figure 1–23. Receiver Channel Datapath
December 2010 Altera Corporation
Receiver PMA
f
f
■
■
For more information about the available settings in each feature, refer to the
Datasheet for Arria II Devices.
Figure 1–22
Figure 1–22. Transmitter Output Buffer
This section describes the Arria II GX and GZ receiver channel datapath architecture.
The sub-blocks in the receiver datapath are described in order from the receiver input
buffer to the RX phase compensation FIFO buffer at the FPGA fabric-to-transceiver
interface.
Figure 1–23
This section describes the receiver PMA modules, which consists of the receiver input
buffer, CDR, and deserializer.
The rx_analogreset signal resets all modules in the receiver PMA block. For more
information about this signal, refer to the
Devices
Receiver-detect capability to support PCIe functional mode—This circuit detects if
there is a receiver downstream by sending out a pulse on the common mode of the
transmitter and monitoring the reflection. For more information, refer to
Mode” on page
Tristate-able transmitter buffer to support PCIe electrical idle—This feature is only
active in PCIe mode to work hand-in-hand with the receiver-detect capability. For
more information, refer to
chapter.
shows the transmitter output buffer block diagram.
shows the receiver channel datapath in Arria II GX and GZ devices.
Programmable
Pre-Emphasis
and V
OD
1–62.
Receiver Channel PCS
“PCIe Mode” on page
Receiver
Detect
Reset Control and Power Down in Arria II
+ VTT -
Arria II Device Handbook Volume 2: Transceivers
50 W
50 W
1–62.
Transmitter
Receiver Channel
Output
Pins
Input Reference
PMA
Clock
“PCIe
Device
Serial Input
Data
rx_datain
1–21
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