EP2AGX190FF35C6N Altera, EP2AGX190FF35C6N Datasheet - Page 193
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EP2AGX190FF35C6N
Manufacturer Part Number
EP2AGX190FF35C6N
Description
IC ARRIA II GX 190K 1152FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX190FF35C6N.pdf
(306 pages)
Specifications of EP2AGX190FF35C6N
Number Of Logic Elements/cells
181165
Number Of Labs/clbs
7612
Total Ram Bits
9939
Number Of I /o
612
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
190300
# I/os (max)
612
Frequency (max)
400MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
190300
Ram Bits
10380902.4
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Chapter 6: I/O Features in Arria II Devices
Design Considerations
Design Considerations
December 2010 Altera Corporation
I/O Termination
Although Arria II devices feature various I/O capabilities for high-performance and
high-speed system designs, there are several other design considerations that require
your attention to ensure the success of your designs.
This section describes I/O termination requirements for single-ended and differential
I/O standards.
Single-Ended I/O Standards
Although single-ended, non-voltage-referenced I/O standards do not require
termination, impedance matching is necessary to reduce reflections and improve
signal integrity.
Voltage-referenced I/O standards require both an input reference voltage (V
termination voltage (V
termination voltage of the transmitting device. Each voltage-referenced I/O standard
requires a specific termination setup. For example, a proper resistive signal
termination scheme is critical in SSTL2 standards to produce a reliable DDR memory
system with a superior noise margin.
Arria II R
optimizing OCT for use in typical transmission line environments, the R
impedance must be equal to or less than the transmission line impedance for optimal
performance. In ideal applications, setting the R
transmission line impedance avoids reflections. You can also use external pull-up
resistors to terminate the voltage-referenced I/O standards such as SSTL and HSTL
I/O standards.
Differential I/O Standards
Differential I/O standards typically require a termination resistor between the two
signals at the receiver. The termination resistor must match the differential load
impedance of the signal line. Arria II devices provide an optional differential on-chip
resistor when you use LVDS.
S
OCT provides the convenience of not using external components. When
TT
). The reference voltage of the receiving device tracks the
Arria II Device Handbook Volume 1: Device Interfaces and Integration
S
OCT impedance to match the
S
OCT
R EF
) and a
6–35
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