EP2AGX190FF35C6N Altera, EP2AGX190FF35C6N Datasheet - Page 187
![no-image](/images/manufacturer_photos/0/0/40/altera_sml.jpg)
EP2AGX190FF35C6N
Manufacturer Part Number
EP2AGX190FF35C6N
Description
IC ARRIA II GX 190K 1152FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX190FF35C6N.pdf
(306 pages)
Specifications of EP2AGX190FF35C6N
Number Of Logic Elements/cells
181165
Number Of Labs/clbs
7612
Total Ram Bits
9939
Number Of I /o
612
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
190300
# I/os (max)
612
Frequency (max)
400MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
190300
Ram Bits
10380902.4
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- EP2AGX45CU17C6N PDF datasheet
- EP2AGX45CU17C6N PDF datasheet #2
- EP2AGX45CU17C6N PDF datasheet #3
- EP2AGX45CU17C6N PDF datasheet #4
- EP2AGX45CU17C6N PDF datasheet #5
- EP2AGX190FF35C6N PDF datasheet #6
- Current page: 187 of 692
- Download datasheet (22Mb)
Chapter 6: I/O Features in Arria II Devices
Termination Schemes for I/O Standards
Figure 6–12. HSTL I/O Standard Termination for Arria II Devices
Note to
(1) Applicable to Arria II GZ devices only.
December 2010 Altera Corporation
External
On-Board
Termination
Termination
OCT
in Bi-
Directional
Pins (1)
OCT
Receive (1)
OCT
Transmit
Figure
6–12:
Series OCT
50
Series OCT 50
Transmitter
Transmitter
Transmitter
Transmitter
Figure 6–12
V
CCIO
100
100
HSTL Class I
50
50
50
50
shows the details of HSTL I/O termination on Arria II devices.
V REF
V REF
50
50
V REF
V TT
V TT
V
CCIO
V
100
CCIO
100
100
100
Series
OCT 50
Receiver
Receiver
Receiver
Receiver
Parallel OCT
Arria II Device Handbook Volume 1: Device Interfaces and Integration
Series OCT
25
Series OCT 25
Transmitter
Transmitter
Transmitter
Transmitter
V
CCIO
100
100
V TT
V TT
HSTL Class II
V TT
50
50
50
50 8
V REF
50
50
V REF
50
50
50
V REF
V TT
V TT
V
CCIO
V
100
100
CCIO
100
100
Receiver
Receiver
Receiver
Receiver
Series
OCT 25
Parallel OCT
6–29
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