EP2AGX190FF35C6N Altera, EP2AGX190FF35C6N Datasheet - Page 156

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EP2AGX190FF35C6N

Manufacturer Part Number
EP2AGX190FF35C6N
Description
IC ARRIA II GX 190K 1152FBGA
Manufacturer
Altera
Series
Arria II GXr

Specifications of EP2AGX190FF35C6N

Number Of Logic Elements/cells
181165
Number Of Labs/clbs
7612
Total Ram Bits
9939
Number Of I /o
612
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
190300
# I/os (max)
612
Frequency (max)
400MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
190300
Ram Bits
10380902.4
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant

Available stocks

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Part Number
Manufacturer
Quantity
Price
Part Number:
EP2AGX190FF35C6N
Manufacturer:
Altera
Quantity:
10 000
Part Number:
EP2AGX190FF35C6N
Manufacturer:
ALTERA
0
Part Number:
EP2AGX190FF35C6N
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5–52
Document Revision History
Table 5–23. Document Revision History
Arria II Device Handbook Volume 1: Device Interfaces and Integration
December 2010
July 2010
November 2009
June 2009
February 2009
Date
PLL Specifications
f
Version
For more information about PLL timing specifications, refer to the
Arria II
Table 5–23
4.0
2.0
3.0
1.1
1.0
Updated for Arria II GX v10.0 release:
Updated for Arria II GX v9.1 release:
Initial release
Devices.
Updated for the Quartus II software version 10.1 release.
Added Arria II GZ devices information.
Updated
Added
Figure
Figure
Added
Added
Minor text edit.
Updated “Clock Regions” and “Arria II PLL Hardware Overview” sections.
Updated Figure 5–44.
Removed sub-regional clock references.
Minor text edit.
Updated Table 5–1.
Updated Figure 5–14.
Updated the “Periphery Clock (PCLK) Networks” and “Cascading PLLs” sections.
Minor text edit.
Updated Table 5–8.
Updated Figure 5–13 and Figure 5–14.
Updated the “PLL Clock I/O Pins” and “PLL Reconfiguration Hardware Implementation”
sections.
shows the revision history for this document.
5–11,
5–27,
Figure
Table
“Clock Sources Per Quadrant”
Table
5–5,
Figure
Figure
5–2,
5–1,
Table
Figure
Table
5–16,
5–38, and
5–7,
5–12,
5–3,
Figure
Table
Figure
Figure
Table
5–18,
5–9,
5–39.
5–4,
5–20, and
and
Changes
Figure
Table
Chapter 5: Clock Networks and PLLs in Arria II Devices
“External Feedback Mode”
Figure
5–11,
5–19,
Table
5–5,
andTable
Figure
5–21.
Figure
December 2010 Altera Corporation
5–24,
5–16.
5–7,
Figure
Figure
Document Revision History
Device Datasheet for
sections.
5–26,
5–15,

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