EP2AGX190FF35C6N Altera, EP2AGX190FF35C6N Datasheet - Page 293

• Manufacturer Part Number: EP2AGX190FF35C6N
• Description: IC ARRIA II GX 190K 1152FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX190FF35C6N

• Number Of Logic Elements/cells: 181165
• Number Of Labs/clbs: 7612
• Total Ram Bits: 9939
• Number Of I /o: 612
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 190300
• # I/os (max): 612
• Frequency (max): 400MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 190300
• Ram Bits: 10380902.4
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 9: Configuration, Design Security, and Remote System Upgrades in Arria II Devices
Fast Passive Parallel Configuration
Figure 9–2. Multi-Device FPP Configuration Using an External Host
Notes to
(1) Connect the pull-up resistor to a supply that provides an acceptable input signal for the Arria II device. For Arria II GX devices, use the V
(2) The MSEL pin settings vary for different configuration voltage standards and POR delay. To connect MSEL[3..0]for an Arria II GX device, refer to
December 2010 Altera Corporation
For Arria II GZ devices, use the V
external host. Altera recommends powering up the configuration system I/Os with V
Table 9–6 on page
Figure
(MAX II Device or
Microprocessor)
External Host
ADDR DATA[7..0]
9–2:
Memory
9–9. To connect MSEL[2..0] for an Arria II GZ device, refer to
You also have the flexibility to synchronize initialization of multiple devices or to
delay initialization with the CLKUSR option. You can turn on the Enable
user-supplied start-up clock (CLKUSR) option in the Quartus II software from the
General tab of the Device and Pin Options dialog box. If you supply a clock on
CLKUSR, it does not affect the configuration process. Arria II devices support an f
125 MHz.
Figure 9–2
This circuit is similar to the FPP configuration circuit for a single device, except the
Arria II devices are cascaded for multi-device configuration.
After the first device completes configuration in a multi-device configuration chain,
its nCEO pin drives low to activate the nCE pin of the second device, which prompts the
second device to begin configuration. The second device in the chain begins
configuration in one clock cycle; therefore, the transfer of data destinations is
transparent to the MAX II device or microprocessor. All other configuration pins
(nCONFIG, nSTATUS, DCLK, DATA[7..0], and CONF_DONE) are connected to every device in
the chain. The configuration signals may require buffering to ensure signal integrity
and prevent clock skew problems. Ensure that the DCLK and DATA lines are buffered for
every fourth device. Because all device CONF_DONE pins are tied together, all devices
initialize and enter user mode at the same time.
All nSTATUS and CONF_DONE pins are tied together and if any device detects an error,
configuration stops for the entire chain and you must reconfigure the entire chain. For
example, if the first device flags an error on nSTATUS, it resets the chain by pulling its
nSTATUS pin low. This behavior is similar to a single device detecting an error.
V
CCIO
CCPGM
10 kΩ
/V
(1)
CCPGM
shows how to configure multiple Arria II devices using a MAX II device.
pin. V
V
CCIO
CCIO
/V
(1)
/V
CCPGM
10 kΩ
CCPGM
GND
must be high enough to meet the V
CONF_DONE
nSTATUS
nCE
DATA[7..0]
nCONFIG
DCLK
Arria II Device 1
MSEL[n..0]
Arria II Device Handbook Volume 1: Device Interfaces and Integration
nCEO
Table 9–7 on page
V
CCIO
CCIO
(2)
/V
/V
CCPGM
CCPGM
IH
specification of the I/O on both the device and the
10 kΩ
.
(1)
9–10.
CONF_DONE
nSTATUS
nCE
DATA[7..0]
nCONFIG
DCLK
Arria II Device 2
MSEL[n..0]
nCEO
MAX
N.C.
CCIO
(2)
9–13
pin.
of