EP2AGX190FF35C6N Altera, EP2AGX190FF35C6N Datasheet - Page 165

• Manufacturer Part Number: EP2AGX190FF35C6N
• Description: IC ARRIA II GX 190K 1152FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX190FF35C6N

• Number Of Logic Elements/cells: 181165
• Number Of Labs/clbs: 7612
• Total Ram Bits: 9939
• Number Of I /o: 612
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 190300
• # I/os (max): 612
• Frequency (max): 400MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 190300
• Ram Bits: 10380902.4
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 6: I/O Features in Arria II Devices
I/O Banks
Table 6–3. Available I/O Pins in Each Arria II GX I/O Bank
December 2010 Altera Corporation
Package
358-pin Flip
Chip UBGA
572-pin Flip
Chip FBGA
780-pin Flip
Chip FBGA
1152-pin Flip
Chip FBGA
Note to
(1) The number of I/O pins include all general purpose I/Os, dedicated clock pins, and dual-purpose configuration pins. Transceiver pins
and dedicated configuration pins are not included in the I/O pin count.
Table
Modular I/O Banks
6–3:
Device
EP2AGX45
EP2AGX65
EP2AGX45
EP2AGX65
EP2AGX95
EP2AGX125
EP2AGX45
EP24GX65
EP2AGX95
EP2AGX125
EP2AGX190
EP2AGX260
EP2AGX95
EP2AGX125
EP2AGX190
EP2AGX260
The I/O pins in Arria II devices are arranged in groups called modular I/O banks.
Depending on the device densities, the number of I/O banks range from 6 to 20.
Table 6–3
3A
22
22
38
38
38
38
54
54
54
54
54
54
70
70
70
70
and
3B
—
—
—
—
—
—
—
—
—
—
—
—
—
—
32
32
Table 6–4
4A
38
38
38
38
42
42
70
70
74
74
74
74
74
74
74
74
show the number of I/O pins available in each I/O bank.
4B
—
—
—
—
—
—
—
—
—
—
—
—
16
16
32
32
(Note 1)
5A
18
18
50
50
50
50
66
66
66
66
66
66
66
66
66
66
Arria II Device Handbook Volume 1: Device Interfaces and Integration
5B
—
—
—
—
—
—
—
—
—
—
—
—
—
—
32
32
Bank
6A
18
18
50
50
50
50
50
50
50
50
50
50
66
66
66
66
6B
—
—
—
—
—
—
—
—
—
—
—
—
—
—
32
32
7A
38
38
38
38
38
38
70
70
70
70
70
70
70
70
70
70
7B
—
—
—
—
—
—
—
—
—
—
—
—
16
16
32
32
8A
22
22
38
38
42
42
54
54
58
58
58
58
74
74
74
74
8B
—
—
—
—
—
—
—
—
—
—
—
—
—
—
32
32
Total
156
156
252
252
260
260
364
364
372
372
372
372
452
452
612
612
6–7