EP2AGX190FF35C6N Altera, EP2AGX190FF35C6N Datasheet - Page 493
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EP2AGX190FF35C6N
Manufacturer Part Number
EP2AGX190FF35C6N
Description
IC ARRIA II GX 190K 1152FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX190FF35C6N.pdf
(306 pages)
Specifications of EP2AGX190FF35C6N
Number Of Logic Elements/cells
181165
Number Of Labs/clbs
7612
Total Ram Bits
9939
Number Of I /o
612
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
190300
# I/os (max)
612
Frequency (max)
400MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
190300
Ram Bits
10380902.4
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- EP2AGX45CU17C6N PDF datasheet
- EP2AGX45CU17C6N PDF datasheet #2
- EP2AGX45CU17C6N PDF datasheet #3
- EP2AGX45CU17C6N PDF datasheet #4
- EP2AGX45CU17C6N PDF datasheet #5
- EP2AGX190FF35C6N PDF datasheet #6
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- Download datasheet (22Mb)
Chapter 2: Transceiver Clocking in Arria II Devices
CMU PLL and Receiver CDR Input Reference Clocking
Figure 2–2. Input Reference Clock Sources Across Transceiver Blocks
December 2010 Altera Corporation
refclk0
refclk1
refclk0
refclk1
refclk0
refclk1
refclk0
refclk1
1
Figure 2–2
in four transceiver blocks on the left side of the EP2AGX260FF35 device.
refclk0 and refclk1 Pins
Each transceiver block has two dedicated refclk pins that you can use to drive the
CMU PLL, receiver CDR, input reference clock, or all three. Each of the two CMU
PLLs and four receiver CDRs within a transceiver block can derive its input reference
clock from either the refclk0 or refclk1 pin.
The refclk pins provide the cleanest input reference clock path to the CMU PLLs.
Altera recommends using the refclk pins to drive the CMU PLL input reference clock
for improved transmitter output jitter performance.
/2
/2
/2
/2
/2
/2
/2
/2
shows the input reference clock sources for CMU PLLs and receiver CDRs
PLL Cascade Clock
PLL Cascade Clock
PLL Cascade Clock
PLL Cascade Clock
Global Clock Line
Global Clock Line
Global Clock Line
Global Clock Line
ITB Clock Lines
ITB Clock Lines
ITB Clock Lines
ITB Clock Lines
6
6
6
6
6
6
6
6
Arria II Device Handbook Volume 2: Transceivers
Transceiver Block GXBL3
Transceiver Block GXBL2
Transceiver Block GXBL1
Transceiver Block GXBL0
Two CMU PLLs
Two CMU PLLs
Two CMU PLLs
Two CMU PLLs
Four RX CDRs
Four RX CDRs
Four RX CDRs
Four RX CDRs
and
and
and
and
2–3
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