EP2AGX190FF35C6N Altera, EP2AGX190FF35C6N Datasheet - Page 511

• Manufacturer Part Number: EP2AGX190FF35C6N
• Description: IC ARRIA II GX 190K 1152FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX190FF35C6N

• Number Of Logic Elements/cells: 181165
• Number Of Labs/clbs: 7612
• Total Ram Bits: 9939
• Number Of I /o: 612
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 190300
• # I/os (max): 612
• Frequency (max): 400MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 190300
• Ram Bits: 10380902.4
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 2: Transceiver Clocking in Arria II Devices
Transceiver Channel Datapath Clocking
Figure 2–14. Receiver Datapath Clocking in Non-Bonded Configurations with Rate Matcher
December 2010 Altera Corporation
Fabric
FPGA
hard IP
hard IP
hard IP
hard IP
PCIe
PCIe
PCIe
PCIe
Non-Bonded Receiver Clocking with Rate Matcher
The following functional modes have non-bonded receiver channel configurations
with rate-matcher:
■
■
■
■
Figure 2–14
configurations with rate matcher.
PCIe ×1
GIGE
Serial RapidIO
Basic with rate matcher
Interface
Interface
Interface
Interface
PIPE
PIPE
PIPE
PIPE
tx_clkout[3]
tx_clkout[2]
tx_clkout[1]
tx_clkout[0]
shows the receiver datapath clocking in non-bonded channel
Channel 3
Channel 2
Channel 1
Channel 0
/2
/2
/2
/2
Receiver Channel PCS
Receiver Channel PCS
Receiver Channel PCS
Receiver Channel PCS
Arria II Device Handbook Volume 2: Transceivers
Ch3
Ch2
Ch1
Ch0
FPGA Fabric-Transceiver Interface Clock
Parallel Recovered Clock
Serial Recovered Clock
Low-Speed Parallel Clock
Transmitter Channel PMA
Transmitter Channel PMA
Transmitter Channel PMA
Transmitter Channel PMA
Receiver Channel
Receiver Channel
Receiver Channel
Receiver Channel
Divider
Divider
Divider
Divider
Clock
Clock
Clock
Clock
Local
Local
Local
Local
PMA
PMA
PMA
PMA
Reference
Reference
Reference
Reference
From CMU1
From CMU0
From CMU1
From CMU0
From CMU1
From CMU1
From CMU0
From CMU0
Clock
Clock
Clock
Clock
Input
Input
Input
Input
PLL
PLL
PLL
PLL
PLL
PLL
PLL
PLL
2–21